2 New ideas, what do you think?

[lumanauw]

The main problem in class(A)B power amp is crossover distortion. Several smart ccts are made by smart people to overcome this. Some uses EF output stage, without using VBE multiplier.
I've got one idea here. I haven't built it, just a concept. I think in this cct there is no VBE conflict. The main idea is that positive signal only changes upper transistors (NPN) without disturbing lower transistor at all, and negative signal only affects lower transistor (PNP).
T1+R3+D1+D2 is forming current source, with drop of D1+D2 as reference for R3. T2+R4+D2+D3 is forming another one. D1+D2+D3 are sourced by 2 ccs, ccs2 and ccs4, because full swing will occur here, so cannot use R loading.
Collector of T2 is connected to ccs1 and R1. Collector of T1 is connected to ccs3 and R2.
Emitor of T1 is connected to D4 and emitor of T2 is connected to D5.
If we put IN4148 for D1 to D5, assume drop of 0V7, then pointA of D4 will be sitting at +0V35 and pointB of D5 is sitting at -0V35, that means D4 and D5 will be conducting very-very small current in steady state (uA in the IN4148 pdf datasheet). Most of the current from R3 and R4 will be passing T1 and T2, because in that voltage, D4 and D5 can be considered "inactive"

When there is a positive signal, it can only pass D5 (cannot pass D4 because reversed). This input current will charge R4 so that I1 from ccs1 become less, and I2 will be rising (because ccs1 giving constant current). I2 will rise voltage drop on R1 that activate T3.
This way, positive signal won't disturb the balance in R2 and T4.

For negative signal, same tracing will occur from D4 to T4 without disturbing R1 and T3. Bias can be adjusted by 1 VR, connected // with D2.

A steady bias will be preserved in the inactive transistor.

D4 and D5 will be working in 0V35 drop only. Will it work? What do you think?

[lumanauw]

This idea is not new, it comes from brilliant work of NP, continued by smart development by PMA.
I just see another possibility of using this NP-PMA. Making a "Current Feedback" power amp. Some said it is a very fast topology compared to voltage feedback.

The 4 transistor arrangement T1-T4 can be seen as "Inverted differential" where the inputs are emitors, and the reference connecting points are their bases. (in ordinary differential, the inputs are their bases and the reference connecting point are their emitors)
So if we put emitors T2 and T4 to ground, it will set the whole 0 point of this amp. Input signal is fed to emitors of T1 and T3.

The output is driving T5 and T6, which is using HAFLER/QSC inverted CT-output. This will gives inverting amplifier.
Since it's an inverting amplifier, the gain ratio is set up by Rfb/Rin, and the 0 offset is maintained by the "inverted differential", by connecting Emitors of T2 and T4 to ground.

Another advantage of this configuration is that the NP-PMA can works in only +/-15V supply, that means very big current (up to 40mA-preserving linearity) can be arranged here without thermal issues.

Another advantage is it is a very short stages from input to output. The "inverted differential" is also acting as a non-turnoff biasing scheme.

Rin and Rfb needs tobe very low for current feedback topology (maybe 100ohm and 1kohm). Then C input needs to be very large. Or we can omit Cinput and put servo here?
Also we also may need a diamond buffer for driving input, since the input will need quite big driving current.

[darkfenriz]

about idea 1
assuming nothing you thought is wrong I see problem with current sources imbalance and not steady (hard to adjust precise enough) bias. And still you have switching in signal path....
just thoughts...

anyway it is very interesting to see good brain work like this
keep your thoughts coming!!
regards

[lumanauw]

Hi, Darkfenriz,

I think you are right. What kind of cct suitable in place of D2? Simple VR or CCS or VBEmultiplier?

[lumanauw]

How to calculate the current needed to drive a current feedback power amp? How to determine the input/feedback resistors in current feedback power amp?