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Old 20th August 2002, 06:54 PM   #1
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Default Mosfet amplifier design

hi Guys, I found this design somewhere, and I know it works because I have seen it. But I'm curious how it works. How is the bias controlled here? I guess the overall gain of the amp can be controller with R59/R52?
Can some of the more experienced designers here post some thaughts?

Thanks!
Peter
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Old 31st August 2002, 02:04 AM   #2
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Smile Hi petervg..

looks like one of vallemans designs....the op-amps linearize the mosfets, while simultaneously controlling standing current in the output stage......

The design is a combination of series applied-shunt derived voltage feedback to the inverting input of ic7, and current feedback applied to the output of said op-amp.

Note that there appears to be an error in the schematic, as T10, and T11 sources should be connected to the positive supply rail.......

Michael, Chigwell, Essex, UK.
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Old 1st September 2002, 12:25 AM   #3
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....notice also, that op amps A1 to A4 require non-zero referenced supply rails......

Vallemans DC offset protection circuit, which you've ommited, is one of the better designed schemes....wouldnt say the same for their SOA protection, (a single slope, linear foldback affair), which i find rather rudimentary...
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Old 1st September 2002, 12:25 PM   #4
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T11, T13 drains should connect to LS+ too.

You could easily extend this amp with more mosfet / opamp sections because the current sharing will be virtually perfect, limited only by the matching accuracy of the source resistors. Variations in threshold voltage and Rdson don't matter a toot. Each fet's opamp forces it to conduct the amount of current it is told. As a result though, the output impedance is sky high because the output stage is a current source, relying on the the overall negative feedback to make it a low impedance voltage source, which is what we really want.

GP.
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Old 1st September 2002, 04:58 PM   #5
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Smile Hi circlotron...

I think you'll find that the output impedance is near zero...the output fets are inclosed in a local feeedback loop defined by ic7 r28, r60....

Think of the whole as one large fet-bjt complimentary feedback pair, (if we neglect A1-A4),....with global feedback implimented by r52, r59.
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