My 'parallel' amplifier

[Alme]

this is my first thread at this forum
I concentrated on car amps last times and here is one of them. It's supposed to be 'better quality' amp with no bias adjustment, FET output stage and ability to drive 2 Ohm, or 4 Ohm in bridge.
I reminded old style BJT 'parallel' output stage known from Soviet articles of 1980s, and implemented it on FET basis. The input stage is some modified of that kind of old style Japanese amplifiers.
Power supply is SMPS PWM converter with primitive stabilization of rails. Those '10V batteries' on simulation schematic are bootstraps for maximum efficiency.
Measured parameters:
output power: 60W @ 4 Ohm,
or 100W @ 2 Ohm (200W @ 4 Ohm bridged);
THD+N: 0,002% @ 20Hz at rated power;
0,002% @ 1kHz at rated power;
0,036% @ 20kHz at rated power;
0,0015% @ 1kHz at 1W into 4 Ohm load.

Any suggestions about further improvement appreciated!

[Alme]

Yep. And in my real p.c.b. there used: Q5=2SD600, Q11=2SB631, X3=IRF9610, X4=IRF610, X1=X2=IRF640, X5=X6=IRF9640.
Two output pairs in parallel because I use single heatsink and silicon insulation.
Bias current is about 200mA each pair and slightly increases during heating.
As soon as I get a photocamera - probably tomorrow - I'll put a p.c.b. photo here.

[jleaman]

your missing some lines in your schematic there Dude. : O)

[Alme]

Really? What lines? Did you open the GIF image in its actual size?

[jleaman]

My bad sorry : ) see it now : O ) so a board design ? what program did you use to build the board ?

[darkfenriz]

interesting VAS , how do we call VAS like this?
output stage seems to work in class B
gate resistors are rather small

best regards

[X.G.]

hi,Alme

your circuit is interesting.it has a very special VAS stage and a MOS- FET diamond buffer...the VAS stage is my first look,could you explain the advantage of it?


X.G.

[Alme]

I see folks primarily are interested in VAS not in output stage

darkfenriz, I don't know how to call such voltage amplifying stage, so let's call it cascoded.
I think this output stage is claccical AB mode, as total bias current is 400-500mA, as I mentioned above.
It doesn't need bias adjustments as long as specified FETs are used from the same manufacturer (in my p.c.b., I installed random lot FETs by IR). Well I agree that bias in this schematic is dependent on threshold of FETs and hence on different types and manufacturers and can be difficult to decrease if needed.

Here I put the original prototype schematic (some values there may be incorrect though). Common emitter VAS has been replaced for common collector one (it's maybe not obvious from the first sight that it's double emitter follower there). Cascode stages left the same.
The main idea was to lower open-loop gain while trying to expand gain-bandwidth. Simulation shows open-loop gain about 5000 decreasing to 3500 at 20kHz (C3=0). With differential stages emitter resistors increased to 330 Ohm, 2600 and 1800, respectively.
By the way you gave me another idea to connect collectors of Q3, Q12 (my sch references) directly to ground - whether it will be any difference there ot not. By now simulation shows open-loop gain degraded by about 10% because of this.

[Alme]

here is its p.c.b. picture. It was first made for higher power amplifier 'conception' with high bias that's why there are some free TO-220 rooms, preamplifier space and even two fans added.
Q1 and Q15 also installed on the heatsink along with all FETs.
I'm aware this p.c.b. is so large that is useless for actual amplifier

[Alme]

here is its power supply section. By now, I removed DC chokes and rewinded transformer for no-PWM operation; now maximum output power strongly depends on input battery voltage.

Unfortunately, all references on p.c.b. do not correspond to schematics shown (schematics taken from simulation program).

***
why I'm asking for advice? Because amplifier shows THD increase linearly with frequency above 1kHz, although slew rate is about 20V/us with frequency correction shown. And I cannot recognize where is main problem - how to overcome this or how to make gates 'moving faster'. I say so about gates because decreasing of R7, R28 values gave me linear decrease in THD at high frequency! these resistors actually define VAS bias current, but its further rise makes Q5, Q11 very hot (dissipation 1W and more). So I suspect FET gate capacitances to cause this problem.