Eliminating capacitor in amplifier series feedback loop

[Hennie]

Some power amp designs eliminate the capacitor in the series feedback path because a good quality capacitor in this critical position needs to have a large value and can therefore be expensive. A DC servo is then used to control the DC offset voltage at the output.

A friend of mine has used the circuit below many years ago. It allows the use of a smaller capacitor (C1) which can then be MKP or similar. R3 must be much smaller than R2 to get a good -3 db at low frequencies. For this reason the circuit works best with FET's in the diff amp. However, useful LF extension can be achieved with BJT's in the diff amp if they are matched and R1 and R2 are precision resistors.

While tweaking a Sony TAF-444ESX amp I noticed that it uses this circuit with a a dual JFET input pair. The capacitor was formed by two 47uF Muse elctrolytics connected in non-polar mode. Although the caps were inside the feedback loop, sound quality still improved when I replaced it with a 10u polycarbonate.

I wonder why this circuit is not used more often since it can eliminate that dreaded electrolytic cap in the feedback circuit. Does anybody have experience with this circuit?

[cunningham]

If not cost, I don't know why anyone would put an electrolitic in the signal or feedback path to begin with. They typically sound sour. Is there any other reason?

[john curl]

Almost everyone puts an electrolytic in the feedback loop. The reason is that it is cheap and effective. Servos, properly designed, are better. Some extreme friends of mine, choose to direct couple, without servos, and live with the voltage drift on the output. This is not easy, most of the time.

[AndrewT]

Hi,
The schematic appears to show a DC gain of about x51 and an AC gain of about x1001. Am I correct?
If so then the amp will generate large DC offsets due to small dc on the input.
regards Andrew T.

[Hennie]

To calculate AC gain short C1:

AC_GAIN=((R2//R3)+R4)/R4, it is about 51

To calculate DC gain remove C1:

It is then a unity gain voltage follower if the input is applied at R1, howeever the usual DC decoupling cap C2 prevents DC response. At DC R3 in series with R4 acts as an output load.

R1=R2 minimizes ofsett voltages.

[peranders]

Originally posted by AndrewT
Hi,
The schematic appears to show a DC gain of about x51 and an AC gain of about x1001. Am I correct?

The DC gain is actually 1! but you have two breakpoints, the last one gives you gain of 1.

[Hennie]

LTSpice Simulation using an op-amp model with input decoupling omitted

The 3-db freq is at 7.8 Hz for the component values posted.

For a JFET input stage R1 and R2 can be increased to 1M to give a -3 db freq of 0,78 Hz.

To improve the low freq cut-off for a BJT input pair R1 and R2 can be increased, but output offset may become an issue. An alternative is to lower R3 and R4. If power dissipation becomes an issue, resistors can be paralleled.

[AndrewT]

Hi,
thanks for explaining the gain.
Q how do you calculate the time constants?
Q is it a 2 pole bass roll off with staggered freqencies?
regards Andrew T.

[sam9]

One of Rod Elliot's articles, perhaps the most recent, discusses the subject. He based it on some SPICE simulations. His conclusion (I won't try to summarize the agument) was that the elimination of this cap can have unpleasant/unfortunate results when certain events occur in the input source.

I don't know enough to say if he is right or wrong, but I think anyone contemplating yanking the cap should at least check it out.

[darkfenriz]

Originally posted by Hennie
The 3-db freq is at 7.8 Hz for the component values posted.

and though it is out of audio range it is still too much- this will bring some phase distortion at LF- not good cause stability/delay issues.
To make border freq. lower should be used bigger resistors, which makes it unable to use in bipolar differential stage.