Symmetrical folded cascode.

[Mr Evil]

I remember playing around with folded cascodes many years ago when I was only just starting to get into audio electronics, thinking that it seemed like a good way to achieve a 2-stage power amplifier. I never managed to make much of them so I forgot all about it. Seeing the subject crop up a few times here recently got me thinking again, so I fired up the simulator and tried to make a fully symmetrical one, just because I can.

I've attached a pic of the circuit I came up with. It doesn't simulate too badly; maybe I'll try building it sometime. In case you're wondering, the current sources are modelled as J510 3.6mA constant current diodes, the BJTs are all BC556/546, the zeners are 20V and the MOSFETs are ECF20N16/20P16. The output stage has a little gain because of the limited output voltage swing of the cascode stage. C2 provides some frequency compensation to (hopefully) keep it stable.

With an extra output stage and a rearranged feedback network, the signal would be balanced throughout, which could be beneficial.

Comments on possible problems would be nice, since I am but a novice compared to some of the designers here.

I'll attach some pics of the sim results down below...

P.S. sorry the images are all rotated 90 degrees, but the forum doesn't like them the other way around.

[Mr Evil]

This is the open-loop frequency response...

[Mr Evil]

And closed-loop. Could probably do with reducing the bandwidth a bit for a practical circuit.

[Mr Evil]

Distortion into 8Ω@30W@1kHz. All below 110dB seems reasonable, although I'm sure it would be worse in reality.

[Mr Evil]

Lastly a square wave into a capacitive load (10nF||8&#937). A little ringing, but that can be removed by increasing the value of C2.

[Konrad]

Folded kaskode... well there is several symetric designs.

Abt your outputstage config: The resistors R10 and R12 is in series emtying the input cap on the mosfets(R7 and R11 for the upper halve). Thus off time is much higher than on time and the bias will bee kind of sliding ( at least sliding in transients). I belive there is som high current flowing thru bouth outputs as they are shifted from on to off.

The output stage gain ideally ((R13+R14)/R14) it is a must to have this gain or reduced feedback when using cfp mos output. The good thing is increased slew.

Your implement of folded kaskode: kolectors of Q10 and Q5 floating? This point has the opposit signal of the Q9 Q4. And is many times seen used as output for bridge or Fully symetric designs.

I dont mean to criticise your design, only let you have som "input"

ragards.

[Mr Evil]

Originally posted by Konrad
...Abt your outputstage config: The resistors R10 and R12 is in series emtying the input cap on the mosfets(R7 and R11 for the upper halve). Thus off time is much higher than on time and the bias will bee kind of sliding ( at least sliding in transients). I belive there is som high current flowing thru bouth outputs as they are shifted from on to off...

Yes, I can see some cross-conduction occuring with very fast signals. How do I stop that?

Originally posted by Konrad
...Your implement of folded kaskode: kolectors of Q10 and Q5 floating? This point has the opposit signal of the Q9 Q4. And is many times seen used as output for bridge or Fully symetric designs...

I did mention that in passing, that it could be made fully balanced, but I thought I would start simple just to see how well it works.

Originally posted by Konrad
...I dont mean to criticise your design, only let you have som "input"...

Not at all! That's why I posted it here.

[thespeakerguy]

I've had better luck biasing the cascode pair with a third transistor, diode connected. A current source biases this transistor, which has a resistor to V+ for the high side. Similar on the bottom. You could use a JFET current source to bias the two sides.

[Konrad]

Originally posted by Mr Evil

Yes, I can see some cross-conduction occuring with very fast signals. How do I stop that?



I did mention that in passing, that it could be made fully balanced, but I thought I would start simple just to see how well it works.



Not at all! That's why I posted it here.

Faster off, a tiny litle help from a transistor. Here in the att: Q5 and Q8.

My first thougts abt your scematic:
The current gain in your org sirc is rather low , i mean vas current gain idealy =1 . The way your zeners is implemented psu ripple is directly set into base rail voltage for your folded circ. swapping current sorces and zeners would bee better.

I dont have the models for your output choise or have sim this sirc so there is still a looooong way before its you can call it ready for som real trial.

[MikeB]

Hi mr.evil !

You might have a look here:
Have you ever succeed in buiding a input stage with current mirror?

But good that you opened a thread for folded cascode...
It's a very interesting topology ! And my prototype of a symetrical
folded cascode is already running !

Mike