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Old 6th September 2004, 01:33 AM   #1
Eva is offline Eva  Spain
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Default Reinventing the N-channel wheel?

I got this while playing a bit with pspice :

Click the image to open in full size.

In simulation it promises to be a class-AB N-channel amplifier circuit with no cross-conduction and very efficient rail-to-rail output, but who knows how well this would work with real devices...

I'll build a prototype as soon as I get some cheap IRF640 or similar [I'm looking also at BUZ32]. The 9V and 12.5V supplies are to be implemented with precise TL431 regulators. The magnitude of the 15V supply actually sets the bias of the output stage so I may implement it with a Vbe multiplier. The regulators referenced to the output will be supplied through classic bootstraping

The gates are driven in an SMPS-ish way forcing allways faster turn-off than turn-on times. This is how the simulation looks when driving the output rail to rail at 10Khz into hard clipping
Click the image to open in full size.


And this is how the simulation looks when operating under normal conditions at 10Khz. Predicted THD is below 0.015%
Click the image to open in full size.
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Old 6th September 2004, 06:47 AM   #2
sajti is offline sajti  Hungary
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Hi Eva,

nice design, but in practice two pairs of IRF640 is not enough with 90V rails. Try to use IRFP260N! Two pairs will take off Your hair, when You turn up the volume

Another idea: I don't think that Q3, and Q6 is necessary. Simply put the bias diodes into the collector of the VAS, and the inverter. I think, that the push-pull emitter followers has enough current amplifying rate.
I guess that the 47 ohm resistors (R2, R5) is checked by the simulation. This resistors looks strange to me I would use two 22 ohms in symmetrical configuration.....

sajti
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Old 6th September 2004, 03:45 PM   #3
Eva is offline Eva  Spain
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I actually want to reduce costs by taking advantage of the absence of second breakdown in MOSFETs, not to expend a fortune in 10 or more pairs of output devices like others did [I wouldn't have enough money to buy such an amount of $5 mosfets anyway...]

I will abandon this project if it doesn't allow for higher output power with less output devices at less cost in comparison with bipolar transistors. Actually I hate MOSFETs in linear applications and I have in mind that four pairs of old & cheap MJ15024/MJ15025 are just enough to reliably drive 4 ohms with +-90 rails provided enough heatsinking. And the main problem in this situation is still SOA since each device in normal operation won't dissipate more than 20W average and 50W in worst case conditions, but 250W devices have to be used in order to get decent SOA

Provided these dissipation figures [20W average, 50W worst case], I'm trying to drive 4 ohms with 90V rails and just 4 pairs of IRF640 or similar cheap TO-220 devices

About Q3 and Q6 : At first they weren't in the schematic but after adding them to the simulation I got 30 extra phase margin at 2,5Mhz and no more parasitistic oscillations. This suggests that the 'weak' output of the VAS is not enough to drive the BD139/BD140 buffers with decent bandwith

The purpose of R2 and R5 is to provide asymetric drive with faster gate discharge and slower gate charge. I borrowed this approach from my SMPS designs and it appears to prevent cross-conduction even in square-wave output conditions

Anyway, I have to test it with real components...
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Old 6th September 2004, 06:25 PM   #4
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Default Please Eva, if you have something alike, using BJT...

Please send me direct mail adress, or, if you prefer, put it in our forum.

Of course i understand your choice, but i like very much the BJT transistor..... those "old man" things.

nanabrother@yahoo.com

regards,

Carlos
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Old 6th September 2004, 06:28 PM   #5
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Default Yes Eva, lower voltage to output can be interesting!

I will be happy to hear your ideas.... lower power, to 8 ohms, from 40 to 65 volts DC to the output.

Having your own design, this way, or making it in the future, please, do not forget me.

Put it here or mail it directly, please

muchas gracias

Carlos
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Old 6th September 2004, 07:18 PM   #6
sajti is offline sajti  Hungary
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Quote:
Originally posted by Eva
I actually want to reduce costs by taking advantage of the absence of second breakdown in MOSFETs, not to expend a fortune in 10 or more pairs of output devices like others did [I wouldn't have enough money to buy such an amount of $5 mosfets anyway...]

I will abandon this project if it doesn't allow for higher output power with less output devices at less cost in comparison with bipolar transistors. Actually I hate MOSFETs in linear applications and I have in mind that four pairs of old & cheap MJ15024/MJ15025 are just enough to reliably drive 4 ohms with +-90 rails provided enough heatsinking. And the main problem in this situation is still SOA since each device in normal operation won't dissipate more than 20W average and 50W in worst case conditions, but 250W devices have to be used in order to get decent SOA

Provided these dissipation figures [20W average, 50W worst case], I'm trying to drive 4 ohms with 90V rails and just 4 pairs of IRF640 or similar cheap TO-220 devices

About Q3 and Q6 : At first they weren't in the schematic but after adding them to the simulation I got 30 extra phase margin at 2,5Mhz and no more parasitistic oscillations. This suggests that the 'weak' output of the VAS is not enough to drive the BD139/BD140 buffers with decent bandwith

The purpose of R2 and R5 is to provide asymetric drive with faster gate discharge and slower gate charge. I borrowed this approach from my SMPS designs and it appears to prevent cross-conduction even in square-wave output conditions

Anyway, I have to test it with real components...

So with 90V rails, and 4ohm load, the maximum dissipation will be about 400W. 4xTO-220 devices are not able handle this power. I would not use them over 25-30W, without dangerous heating...
The IRFP 260N costs about 75% of MJ15024 in my country. This device has TO-247 package, and rated to 300W at 25 degree.
Please note my advice. I killed lot of IRF devices, in class A power follower project, with about 30W dissipation.
For driver position You can use BC639/640. They are same as the BD139/140, but with smaller package, and smaller internal capacitance. I think that BC546B/556B also good for this position. I would use one more diode to set well defined current for the push-pull drivers. This also helps to run them in class A...

sajti
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Old 6th September 2004, 08:27 PM   #7
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I would say you are about to dissipate just over 600 Watts total with 90V rails and 4 Ohms load.

Look at this curve:

Click the image to open in full size.

The black curve shows output power as a function of peak output voltage. At 40 V this example gives out 100 Watts (or we can say 100%).

The purple curve shows the heat dissipation, which is at most powers
around 60 Watts. (Or 60% of the max RMS output).

The interesting thing is that this curve can be translated to any class A/B output stage, and in case of 90V / 4 Ohms load the peak output power (providing no rail loss) is 1018 Watts RMS. So according to this the heat to be dissipated is some 60% of 1018 W or around 600 Watts.

I would agree that IRF640's are too weak for this task alltogether, but a few pairs of IRFP260N or maybe IRFP250N (which cost only little more than IRF640) will do the job nicely.
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Old 7th September 2004, 12:37 AM   #8
Pafi is offline Pafi  Hungary
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Eva!

I send you a dozen (or two) of PSMN070-200 (200V 250W), if you promise to send me the docs (PCB) of final, well-working design! Use min. 6 pcs of them per chanel!
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Old 7th September 2004, 01:50 AM   #9
djk is offline djk
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I wish I had an easy way to post a sketch, this will make more sense if you draw it out on paper as I go on.

Draw a push-pull pair, an NPN with its emitter connected to the emitter of a PNP, the bases tied together through a pair of bias diodes.

The emitters are connected to the gate of a P-channel FET.

The collector of the NPN and the source of the P-channel FET are connected to the + rail.

The base of the PNP is connected to the collector of an NPN wired as a level shift (cascode).

The emitter of the NPN level shift goes through a resistor to the output of an opamp.

The + voltage feeding the opamp also drives the base of the NPN level shift.

Another resistor goes from the emitter of the NPN level shift to the drain of the P-channel FET.

Mirror image everything on the output of the opamp.

Some connections eliminated for clairity.

I'm using an AD842, but any good opamp should work.

You can use a large value gate resistor between the push-pull pair and the FET, and parallel it with a diode with 4R7 in series.

The PNP of the push-pull pair sucks all the gate charge out through the diode and 4R7 resistor.

This is, of course, basic inverter technology too.

If you can keep the FETs cool, 200W out of one pair is possible.

I have no problems with 7S square waves, they look great.
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Old 12th February 2006, 05:57 PM   #10
Eva is offline Eva  Spain
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After almost a year and half of inactivity, I have decided to work a little more into this project.

Currently, I have a working prototype and this is how it looks:
Click the image to open in full size.

Another picture:
Click the image to open in full size.

That prototype currently uses two IRF640 as output devices, works with +-18V regulated rails and puts a bit more than +-16V into 4 ohms (actually a 3.3 ohm speaker). It no longer oscillates, even when the output is coming out of clipping.

One of its funny features is the CFP output bipolar/N-channel-MOS stage. One of its advantages is that changes in Vgs thresold over temperature are automatically corrected. In practice, if I adjust the bias current to 60mA while the heatsink is at approx 15C and then I use the amplifier until the heatsink is at approx 60C, the bias only rises to 90mA. Note that there is *no* thermal feedback mechanism and the temperature of the heatsink is not sensed in any way.

The schematic has changed substantially, altough it has still a lot in common with the old one at the top of the thread. I have decided to discard PSpice and work directly on a real prototype because the simulation mismatches are just unacceptable (I know the models are the ones to blame).
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