Reinventing the N-channel wheel?

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I got this while playing a bit with pspice :

An externally hosted image should be here but it was not working when we last tested it.


In simulation it promises to be a class-AB N-channel amplifier circuit with no cross-conduction and very efficient rail-to-rail output, but who knows how well this would work with real devices...

I'll build a prototype as soon as I get some cheap IRF640 or similar [I'm looking also at BUZ32]. The 9V and 12.5V supplies are to be implemented with precise TL431 regulators. The magnitude of the 15V supply actually sets the bias of the output stage so I may implement it with a Vbe multiplier. The regulators referenced to the output will be supplied through classic bootstraping

The gates are driven in an SMPS-ish way forcing allways faster turn-off than turn-on times. This is how the simulation looks when driving the output rail to rail at 10Khz into hard clipping
An externally hosted image should be here but it was not working when we last tested it.



And this is how the simulation looks when operating under normal conditions at 10Khz. Predicted THD is below 0.015%
An externally hosted image should be here but it was not working when we last tested it.
 
Hi Eva,

nice design, but in practice two pairs of IRF640 is not enough with 90V rails. Try to use IRFP260N! Two pairs will take off Your hair, when You turn up the volume :D

Another idea: I don't think that Q3, and Q6 is necessary. Simply put the bias diodes into the collector of the VAS, and the inverter. I think, that the push-pull emitter followers has enough current amplifying rate.
I guess that the 47 ohm resistors (R2, R5) is checked by the simulation. This resistors looks strange to me I would use two 22 ohms in symmetrical configuration.....

sajti
 
I actually want to reduce costs by taking advantage of the absence of second breakdown in MOSFETs, not to expend a fortune in 10 or more pairs of output devices like others did [I wouldn't have enough money to buy such an amount of $5 mosfets anyway...]

I will abandon this project if it doesn't allow for higher output power with less output devices at less cost in comparison with bipolar transistors. Actually I hate MOSFETs in linear applications and I have in mind that four pairs of old & cheap MJ15024/MJ15025 are just enough to reliably drive 4 ohms with +-90 rails provided enough heatsinking. And the main problem in this situation is still SOA since each device in normal operation won't dissipate more than 20W average and 50W in worst case conditions, but 250W devices have to be used in order to get decent SOA

Provided these dissipation figures [20W average, 50W worst case], I'm trying to drive 4 ohms with 90V rails and just 4 pairs of IRF640 or similar cheap TO-220 devices

About Q3 and Q6 : At first they weren't in the schematic but after adding them to the simulation I got 30º extra phase margin at 2,5Mhz and no more parasitistic oscillations. This suggests that the 'weak' output of the VAS is not enough to drive the BD139/BD140 buffers with decent bandwith

The purpose of R2 and R5 is to provide asymetric drive with faster gate discharge and slower gate charge. I borrowed this approach from my SMPS designs and it appears to prevent cross-conduction even in square-wave output conditions

Anyway, I have to test it with real components...
 
Eva said:
I actually want to reduce costs by taking advantage of the absence of second breakdown in MOSFETs, not to expend a fortune in 10 or more pairs of output devices like others did [I wouldn't have enough money to buy such an amount of $5 mosfets anyway...]

I will abandon this project if it doesn't allow for higher output power with less output devices at less cost in comparison with bipolar transistors. Actually I hate MOSFETs in linear applications and I have in mind that four pairs of old & cheap MJ15024/MJ15025 are just enough to reliably drive 4 ohms with +-90 rails provided enough heatsinking. And the main problem in this situation is still SOA since each device in normal operation won't dissipate more than 20W average and 50W in worst case conditions, but 250W devices have to be used in order to get decent SOA

Provided these dissipation figures [20W average, 50W worst case], I'm trying to drive 4 ohms with 90V rails and just 4 pairs of IRF640 or similar cheap TO-220 devices

About Q3 and Q6 : At first they weren't in the schematic but after adding them to the simulation I got 30º extra phase margin at 2,5Mhz and no more parasitistic oscillations. This suggests that the 'weak' output of the VAS is not enough to drive the BD139/BD140 buffers with decent bandwith

The purpose of R2 and R5 is to provide asymetric drive with faster gate discharge and slower gate charge. I borrowed this approach from my SMPS designs and it appears to prevent cross-conduction even in square-wave output conditions

Anyway, I have to test it with real components...


So with 90V rails, and 4ohm load, the maximum dissipation will be about 400W. 4xTO-220 devices are not able handle this power. I would not use them over 25-30W, without dangerous heating...
The IRFP 260N costs about 75% of MJ15024 in my country. This device has TO-247 package, and rated to 300W at 25 degree.
Please note my advice. I killed lot of IRF devices, in class A power follower project, with about 30W dissipation.
For driver position You can use BC639/640. They are same as the BD139/140, but with smaller package, and smaller internal capacitance. I think that BC546B/556B also good for this position. I would use one more diode to set well defined current for the push-pull drivers. This also helps to run them in class A...

sajti
 
I would say you are about to dissipate just over 600 Watts total with 90V rails and 4 Ohms load.

Look at this curve:

An externally hosted image should be here but it was not working when we last tested it.


The black curve shows output power as a function of peak output voltage. At 40 V this example gives out 100 Watts (or we can say 100%).

The purple curve shows the heat dissipation, which is at most powers
around 60 Watts. (Or 60% of the max RMS output).

The interesting thing is that this curve can be translated to any class A/B output stage, and in case of 90V / 4 Ohms load the peak output power (providing no rail loss) is 1018 Watts RMS. So according to this the heat to be dissipated is some 60% of 1018 W or around 600 Watts.

I would agree that IRF640's are too weak for this task alltogether, but a few pairs of IRFP260N or maybe IRFP250N (which cost only little more than IRF640) will do the job nicely.
 
I wish I had an easy way to post a sketch, this will make more sense if you draw it out on paper as I go on.

Draw a push-pull pair, an NPN with its emitter connected to the emitter of a PNP, the bases tied together through a pair of bias diodes.

The emitters are connected to the gate of a P-channel FET.

The collector of the NPN and the source of the P-channel FET are connected to the + rail.

The base of the PNP is connected to the collector of an NPN wired as a level shift (cascode).

The emitter of the NPN level shift goes through a resistor to the output of an opamp.

The + voltage feeding the opamp also drives the base of the NPN level shift.

Another resistor goes from the emitter of the NPN level shift to the drain of the P-channel FET.

Mirror image everything on the output of the opamp.

Some connections eliminated for clairity.

I'm using an AD842, but any good opamp should work.

You can use a large value gate resistor between the push-pull pair and the FET, and parallel it with a diode with 4R7 in series.

The PNP of the push-pull pair sucks all the gate charge out through the diode and 4R7 resistor.

This is, of course, basic inverter technology too.

If you can keep the FETs cool, 200W out of one pair is possible.

I have no problems with 7µS square waves, they look great.
 
After almost a year and half of inactivity, I have decided to work a little more into this project.

Currently, I have a working prototype and this is how it looks:
An externally hosted image should be here but it was not working when we last tested it.


Another picture:
An externally hosted image should be here but it was not working when we last tested it.


That prototype currently uses two IRF640 as output devices, works with +-18V regulated rails and puts a bit more than +-16V into 4 ohms (actually a 3.3 ohm speaker). It no longer oscillates, even when the output is coming out of clipping.

One of its funny features is the CFP output bipolar/N-channel-MOS stage. One of its advantages is that changes in Vgs thresold over temperature are automatically corrected. In practice, if I adjust the bias current to 60mA while the heatsink is at approx 15ºC and then I use the amplifier until the heatsink is at approx 60ºC, the bias only rises to 90mA. Note that there is *no* thermal feedback mechanism and the temperature of the heatsink is not sensed in any way.

The schematic has changed substantially, altough it has still a lot in common with the old one at the top of the thread. I have decided to discard PSpice and work directly on a real prototype because the simulation mismatches are just unacceptable (I know the models are the ones to blame).
 
Breadboards are evil. The prototype has several compensation capacitors (a total of 7, I think) whose optimum value may change a bit for the PCB version. Anyway, by employing proper layout techniques (the stuff I learn everyday from my SMPS prototypes) stable amplifiers may be built into breadboards, even HEXFET CFPs.

Note that the output devices, the current sense resistors, the output zobel and the supply decoupling capacitor (a single 10uF one between +Vcc and -Vcc since the circuit does not have a power ground connection) are all placed very close to the output devices and inserted in the same breadboard rows. Also, the area of the loops into which high currents flow have been reduced to the minimum, and the last stage of the gate drivers is just in front of the output devices. On the other hand, the area of small signal loops carrying less than 5mA is irrelevant.

By the way, I have replaced two resistors by current sources and I have added RC networks to reduce the gain at HF. As a result, CFP feedback is much stronger at audio frequencies and I can no longer measure any substantial bias current change between 15ºC and 60ºC heatsink temperature. The drawback is that each gate drive cell now requires 5 small signal transistors and 6 or 8 1N4148 diodes, but indeed the gates are well controlled :D
 
I was just reading your design goals and SOA issues on bipolars... have you ever considered bipolar-MOS cascodes in the output stage? Dimensioning it right makes it possible to use the bipolars up to their maximum current, but there are issues to solve, like providing proper paths to charge/discharge the gate capacitance and collector capacitance of the MOSFET. Not obviously, this combo has less rail loss than MOSFETs alone, because the cascode is self-bootstrapping, and only the BJTs define rail loss.
 
Yes, I'm using resistors in the current version, but they are not exactly source resistors but rather current sense resistors. The prototype now looks more or less like that:

An externally hosted image should be here but it was not working when we last tested it.



It's quite weird but each gate drive cell asks for different frequency compensation, at least in the breadboard. The positive cell has less phase margin, maybe due to the current mirror, while the negative cell is faster (probably due to the folded cascode).
 
Eva said:
[BJT-MOS cascode output
ilimzn: could you draw it?

Here is an example - of course, this one uses 'complementary' MOSFETs and BJTs.
Note that Cbc and Cgs, drawn in the pic, are actually the internal capacitances of the BJT and MOSFET. For LAPT transistros such as 2SC2922, 2SC5200 etc, Cbc is not small, neither is reverse collector leakage, but even so, typical Cgs of a MOSFET in the position as drawn will overwhelm both, essentially there is no path for the Cgs to discharge or the MOSFET remains 'stuck' on, and the cacode does not work.
Because of this you have to add Rg and/or Rds as shown in the lower part of the drawing.
The cascode voltage sources can of course be capacitors in a bootstrap arrangement. The voltage on them defines the maximum voltage the BJTs will see across C-E, and in order to be inside the SOA and get good gain, and accounting for the required Cgs of the MOSFET, this will usually be about 10-20V. As long as this voltage is at least somewhat below 20V, the MOSFETs do not need extra gate protection zeners, and can be driven into Rdson region, by the gate voltages being bootstrapped over the rail voltages, so you get very little rail loss.
Even so, gate zeners can be used on the MOSFETs to provide current limiting. A remote way to short the MOSFET gate to source can be used to switch on/off the output stage completely, eliminating the use of relays for output protection.
As amp power goes up, over about 35V per rail, most dissipation has to be endured by the MOSFET, and they can easily be paralleled for that, or more current. Since gate drive is not a problem (it's driven from the output of the amp where current is abundant) very large MOSFETs can easily be used.
 

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I have tried the prototype with +-24V rails and it works fine, so what we have now is a nice but complex 60W/4ohm N-channel amplifier. I'm considering trying other output devices that I have handy, like IRF520, IRF540 and IRFZ44, just to know how they behave before going into higher rails. I also have a few IRFP450 and IRFP460, but these are TO-247 and don't fit to the breadboard. Would a single pair of IRF640 survive driving a 4 ohm reactive load (a bass horn) with +-40V rails provided enough cooling? :D:D:D (I'm afraid we are going to know it soon).


ilimzn:

That's a smart way to take advantage of the dissipation capabilities of MOS devices without messing with gate drive circuits and frequency stability issues as I did :)
 
:idea:
What if you flipped the mosfets around and used seperate drive circuits(diff + EF/w current source; mosfet as output, -fb from drain) for each one, + & -? Similar to guru's SKA, with a DC offset to set the Vce of the BJT. This way you could get rail to rail and have it "regulated" as far as the BJT is concerned. if you can keep it stable...:smash:

Add a lower rail voltage and a couple of Schottkys and you have class G.:dodgy:
 
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