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Old 19th February 2006, 03:36 PM   #51
dimitri is offline dimitri  United States
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eva, pls check your box
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Old 19th February 2006, 03:42 PM   #52
Eva is offline Eva  Spain
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Concerning three diode biasing, I will consider it for the PCB, because the breadboard is full now in this zone and redoing it is a mess

I use these current limiting approaches because, as this is not a standard topology, the devices being protected won't have any chance to saturate when clipping.

Q17 is protected by Q45, and Q19 by D... whatever , because otherwise this gate drive cell will enter into phase inversion and will oscillate during clipping. If the current is not limited, the Vgs of the output device will start to decrease after a certain current level is reached in Q45 due to the voltage drop that it will cause in R43 and R18 (limiting the amount of gate drive while more is asked). Also, allowing the small transistors to saturate deeply produces lousy clipping behaviour (oscillation).

The same happens with the VAS (Q40 and Q15) and Q18/Q42. These transistors are bootstrapped, thus they don't saturate during clipping, and the cascodes are rated at only 50mA but higher currents could be reached if no protections were adopted. Q46 also protects the B-E junction of Q22 from reverse breakdown.

As a result, clipping does not cause any stress on the circuit (I'm a bit PA-minded and I have seen a lot of equipment being abused and destroyed, sometimes I even had to repair it later, so good behaviour under severe overdrive is one of my goals). The circuit takes only a few microseconds to recover into full linearity.
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Old 19th February 2006, 04:41 PM   #53
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Another question. I see that from VBE multiplier to next stage, you don't use base stoppers at all. How can you do that?
What is the "trick" to not have base stoppers from VBE multiplier to the next stage (pre-driver or driver bases)?

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Old 19th February 2006, 07:27 PM   #54
Eva is offline Eva  Spain
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I seldom use base stopper resistors because my circuits are usually stable without them, and when I run into any oscillation issue I usually fix it with capacitors instead. Also, my VAS does not use the standard miller compensation (that may cause the output stage to interact with the VAS local feedback system and may require stopper resistors), instead it has a RC network in its base that fixes the current gain to unity at high frequencies (thus bypassing the VAS) and a small capacitive load that causes that output current to produce a rolling off voltage (a pole, plus a zero+pole form the RC network). It does not work in the same way as the single-pole conventional system.

As it was shown, this approach also produces low distortion when operated without any global feedback.
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Old 21st February 2006, 12:34 AM   #55
Eva is offline Eva  Spain
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Update:

I have been tweaking a bit the frequency compensation networks and that's what I finally got. This is how a 10Khz square wave driving a 10ohm resistor looks:
Click the image to open in full size.


And this is a 100Khz square wave driving the same 10 ohm resistor. I had to reduce the voltage in order to prevent the resistors of the output HF dummy loads from toasting instantaneously:
Click the image to open in full size.
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Old 21st February 2006, 07:37 AM   #56
AndrewT is offline AndrewT  Scotland
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Hi Eva,
the oscilloscope plots are real test loads? not simulations?
Can you describe you test setup/equipment? or refer us to a previous post?
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Old 21st February 2006, 08:51 AM   #57
Eva is offline Eva  Spain
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All my oscilloscope captures are acquired from real prototypes with a HAMEG HM-407-2 in 100Ms/s digital storage mode, and transferred to the computer through RS-232. As I have mentioned several times through the thread, PSpice simulations of MOSFET linear circuits are of little use because most of the models available are almost ideal and doesn't even reflect non-linear capacitances, so they yield very inaccurate and optimistic results.

The amplifier prototype is currently breadboarded and a couple of pictures are shown in page 1 of that thread. Current schematic is similar to the last one that I published with minor changes (mostly to enable global feedback again after the crazy 10Khz open-loop test, and a 68pf phase-lead capacitor across the 10K feedback resistor).

The power supply is based in LM317 and LM337 and currently adjusted to +-24V. Practical DC current limit is 2A altough higher AC peaks are allowed due to storage capacitors. While this limits seriously the output power, it has prevented several disasters due to supurious contacts in the breadboard. The test loads are 10 ohm 50W power resistors with some heatsinking, that I combine to get other smaller values (2.5ohm, 3.3ohm, 5ohm).

The sine wave signals are generated through a computer sound card (either SB-AWE32 or VIA built-in chipset) and are bursted with a 10% duty cycle to allow testing with a 2.5 ohm load without folding the power supply. The square wave signals are generated with a battery-powered bread-boarded CD4049 CMOS hex-inverter configured as an oscillator, and since I can't use bursting here, test load has to be 10 ohm to avoid folding the small bench PSU (I have to build a decent generator one of these days).

Feel free to ask if you want more details.
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Old 21st February 2006, 11:01 AM   #58
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Quote:
Originally posted by Eva
I have to build a decent generator one of these days
Seems to be common with you geenies.

Can you explain to a dork how you can get round using many OP devices on +/-90V, will forcing it in Pseudo-Class A not make it even more difficult ?
And the obvious: you intend to post the final layout for us to rob your IP ?
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Old 21st February 2006, 11:45 AM   #59
Eva is offline Eva  Spain
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If you compare the pseudo-class-A schematic with the normal schematic, the difference is very subtle. The output stage is just the same, the only thing that changes is the class B splitter. My output stage works as two voltage controlled current sources, so the only thing that has to be done to keep it biased continuously is to provide a minimum drive voltage to the bases of Q17 and Q42 by means of two Vbe multipliers (that also compensate for temperature drift in Q17, Q42 and in the associated current sources of each gate drive cell). Anyway, I have serious doubts about the improvements that this solution could bring so I'm not likely to implement it.

To use higher rails I will obviously have to use more output devices. This brings two alternatives. One is to use matched devices with small additional source resistors and keep just two gate drive cells. The other solution is to use one gate drive cell for each output device and avoid completely the chore of matching, since each gate drive cell will drive each device to provide exactly the same current level, even when different models of output devices are employed In both cases the pseudo-class-A is implemented in the same way, since the bases of the "Q17" and "Q42" of each gate drive cell can be driven with the same bias setting voltage.

I've started to lay out a PCB with four gate drive cells. I want to know how much power can I get reliably from 4 TO-220 output devices.

Concerning other people copying my design... Well, it may happen. Actually I would be glad to see people building my stuff for personal use. Obviously, there are other people (salesmen) that are only focused on making profit from anything they get in their hands, but they already have their star producs and an enormous pride, so they are not likely to copy anything from me
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Old 22nd February 2006, 04:10 PM   #60
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Hi, EVA,

Since you like to squeeze tremendous power from a pair of TO220 device, why don't you make a classD with your "drive cell"?
You have sufficient knowledge, even to make a good self oscilating one
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