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Old 13th February 2006, 02:52 PM   #21
Eva is offline Eva  Spain
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CBS240: Could you draw it? I don't understand the description.
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Old 13th February 2006, 03:26 PM   #22
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Ahh, what do I see, a XQ derivative!

Ok, so you use S-"resistors", those 200 nH inductances in series in your schematic make me think you use a "one-turn" component commonly used by SMPS people, why do I think so?

Wouldn't you consider replace lower side FET's with IRF9540?
But you probably want to go the N-ch way anyhow...


Your latest schematic is very complex, I'm thinking especially upper and lower CFP's which is not working the same way either.
You have double gain stages in your CFP, is that really good, at least the upper one?
The lower one consists partially of something looking like a folded cascode.

Cheers Michael
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Old 13th February 2006, 04:00 PM   #23
ilimzn is offline ilimzn  Croatia
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Quote:
Originally posted by Eva
Would a single pair of IRF640 survive driving a 4 ohm reactive load (a bass horn) with +-40V rails provided enough cooling? (I'm afraid we are going to know it soon).
Ehmmm, in short - no. Maybe, assuming a non-reactive load and special care taken to cool the MOSFETs (like separate heatsinks so you can avoid mica insulators, and a copper core fan cooled heatsink. One of the most 'extreme' I've seen involved soldering a MOSFET onto a copper cored Athlon CPU cooler.
IRFP parts are MUCH better for this. Make a comparison of the IRF640 and IRFP240 for SOA, you will be amazed at the differences, although it's almost exactly the same silicon inside!

Quote:
ilimzn:
That's a smart way to take advantage of the dissipation capabilities of MOS devices without messing with gate drive circuits and frequency stability issues as I did [/B]
Well, yes and no - it is not trivial, but it does work and makes a lot of things easyer. I can't claim it as mine, though - Sony uset that in some of their VFET (yes, the power JFET transistors again...) amps, but since the VFET is a depletion device, you only have to tie the gate to the output and you are set.
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Old 13th February 2006, 06:27 PM   #24
Eva is offline Eva  Spain
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Quote:
Originally posted by Ultima Thule
Ahh, what do I see, a XQ derivative!

Ok, so you use S-"resistors", those 200 nH inductances in series in your schematic make me think you use a "one-turn" component commonly used by SMPS people, why do I think so?
What is XQ?

Those 200nH are just the estimated leakage inductance of a standard 0.25ohm wirewound resistor. Circuit behaviour at RF changes a lot when it's not considered Anyway, PSpice is not going to show much of the actual circuit behaviour


Quote:

Wouldn't you consider replace lower side FET's with IRF9540?
But you probably want to go the N-ch way anyhow...
It would be too easy this way, and N-ch and P-ch fets have very dissimilar transfer characteristics. Furthermore, both the direct and the inverting cell use the same number of transistors, so the circuit would look much like the same.


Quote:

Your latest schematic is very complex, I'm thinking especially upper and lower CFP's which is not working the same way either.
You have double gain stages in your CFP, is that really good, at least the upper one?
The lower one consists partially of something looking like a folded cascode.

Cheers Michael
Yes, it's complex but I like it because all the complexity is made out of low-cost small signal devices and because it does not require any thermal compensation. In this last version with current sources I adjusted output stage bias current to 100mA with +-18V rails while the heatsink was at 15ļC or so, then I measured it back later after playing for a while with +-24V rails and the heatsink too hot to be touched... Still 100mA

Altough both CFP cells are not identical, they both should show unity current gain. The upper one just mirrors the error current because it's required to do so while the lower one uses a folded cascode for level shifting that has also inherent unity current gain, thus the same current level flowing through the 22 ohm emitter resistors is applied to the bases of the totem pole gate drivers. The AC voltage gain is set by the RC networks, and the DC voltage gain is... Very high

The diodes in paralell with the gate resistors may seem a bit weird, but clipping recovery behaviour improves a lot when they are added. Note that 1N4148 types are very convenient for that purpose because they are slightly resistive

One of the things that I have to improve is the current sources of the lower gate drive cell, because the current through the 10k resistor is modulated when the lower rail is bootstrapped (near clipping). This causes the voltage drop across the 1N4148 diodes to change and in effect modulates the current sources, thus reducing linearity and gain.
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Old 13th February 2006, 07:21 PM   #25
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Ilimzn,

what cascode voltages have you thought of?

For those who are interested NP holds an old patent for cascoded OP.

Eva,

X=cross Q=quad..
It's interesting to see you adopt the XQ into yor design!

Oh, yes of course both have the same current gain, or so.. but what I meant the CFP's have a huge and a bit different gain is the internal voltage gain, for instance Q 19 with Q36 formed as a CCS has huge gain.
Q17 has a bit more gain than Q18 due to R43, isn't that correct?

You said earlier:
Quote:
The positive cell has less phase margin, maybe due to the current mirror
..you mean Q7 & Q8, just trying to follow you here.
But isn't this due to the folded cascode in the lower CFP cell, are you able to check the propagation delay for respective CFP cell?

Cheers Michael
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Old 14th February 2006, 12:39 AM   #26
ilimzn is offline ilimzn  Croatia
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Quote:
Originally posted by Ultima Thule
Ilimzn,
what cascode voltages have you thought of?
It depends on several factors.
Depending on the output BJT and MOSFET used, you want to utilise their power dissipation capability the best you can. So, logically, you would be looking towards about half the rail voltage for an even split between BJT and MOS, but depending on parts selected (perhaps by some of the criteria below), you may want a different split - although, typically, it will be the MOSFET that will take the brunt of the dissipation due to second breakdown immunity.
Then, the above has to be adjusted taking into account the Vgs for the maximum output current and drop on the BJT emitter resistors, as the BJT will be seeing that much less C-E compared to the cascode voltage.
Further, you also need to adjust for BJT SOA - at maximum BJT current you want your C-E voltage to be below the value where the second breakdown limit is imposed. This will typically be something from a few V to perhaps 15-20V.
Finally, you need to ensure that the Vgs of the MOSFET remains below it's maximum permitted value when the BJT is driven into saturation, which for most MOSFETs limits you to 20V.
You may also want to limit the Vgsmax in order to provide a current limit (non-foldback). It is possible to limit this by selecting the cascode voltage, but that way it will be quite low (5-8V for VMOS).
All in all, for typical transistors you end with voltages between 5 and 20V.
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Old 14th February 2006, 04:11 AM   #27
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Quote:
Originally posted by Eva
CBS240: Could you draw it? I don't understand the description.

Hi Eva,

I bread-boarded a circuit basically similar to this, but then I had to go work out of state for 3 months,(7 weeks yet to go) so I have not had a chance to get any real experimentation done. Quite sure improvements could be made. However, I was able to keep the phase of the output from the FET right on top of the ďaudioĒ at 15Khz,(that was as fast as I could get my cheap P-O-S op-amp oscillator to go and still get a smooth, stable sine wave) but Iím sure it will go to 20Khz.(still donít have a function generator ) If you just use the FET as a follower from the audio, there will be a large phase shift due to gate capacitance and the wave forms will not line up. Local feedback compensates for this. C1/C2 in my circuit was 4.7nf to stabilize oscillations, but Iím sure this is dependent on the devices used and may be better placed as well.
V1 is regulated and V2 is high current, but around the same voltage. R sets a DC bias on Q1 so that DC x gain(10) = Vce of Q14. The audio amplitude will be the same as Vout, but with a DC component, Vce. I did not use the FET for full wave though, but used a lower drive supply and two rectifier diodes in a class G style, but I donít see why it wouldnít work for full wave. By keeping the Vce of Q14 lower but dynamic, the SOA isnít such a factor to the BJTs. Personally Iím with you on using BJTs for linear operations over FETs. If the FET output is slightly non-linear here, it isnít such a problem to the actual output as long as there is no significant HF components as they will pass right through the BJT.

BTW, check out FQH90N15, and FQA36P15 from Farchild.(http://www.Fairchildsemi.com) They are new and have quite extensive SOA. I plan to get some of these when I return home....if that ever happens.
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Old 14th February 2006, 05:27 AM   #28
Eva is offline Eva  Spain
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Ultima Thule:

Yes, I decided to adopt my own non-latching and non-phase-reversing version of the cross quad due to its linearity. Mine is biased with 1mA and has 68 ohm degradation resistors, so it can whitstand more than 100mV of input differential voltage while still producing a perfectly linear output current. With a global voltage gain of approx 33, this means that the output voltage of the amplifier may deviate more than 3.3V from the expected value without overdriving the LTP or forcng it to produce non-linear error signals. This may be clearly observed during clipping, as the LTP turns off and on progressively while providing a very smooth error signal to the VAS.

That overdrive feature is highly desirable in non-class-A amplifiers employing vertical MOSFET output devices due to the *miserable* linearity of these devices, particularly at high frequencies and in the zero current crossing region, that may lead to high frequency glitches. The LTP must try to correct that without being disturbed. Note that the current gain of the VAS is strongly reduced at HF due to R35 and C8, so during any output glitch it may also take even 1mA of error signal without being overdriven itself.

Also, what I call the positive cell is the one driven by Q17, and the negative is the one driven by Q18. Both provide unity current gain and very high voltage gain to the gate at low frequencies due to Q19/Q36 and Q20/Q22 acting as current sources. The main difference, I think, is that in the positive cell Q19 is driven by the base and working in common emitter, while Q22 of the lower cell is being driven by the emitter and working in common base. Also, the layout of the positive cell in the breadboard is a bit more clumsy, so this may be reducing phase margin.

Oh, by the way, I'm considering driving the output stage into fake class-A by keeping both gate drive cells biased all the time, this would be a great improvement to linearity. Since the emitter currents of Q17 and Q18 are almost constant at audio frequencies, thus yielding constant Vbe and voltage drop across the 22 ohm resistors, the task is somewhat simpler than with conventional bipolar output stages. Conceptually, it would be achieved with two voltage sources, one between the base of Q17 and the output, and other betweem the output and the base of Q18, that should provide a minimum voltage (adjustable) that increases alternatively in one or the other depending on the VAS sourcing or sinking current. This may produce longer cross-conduction spikes when recovering from clipping, though (currently they are just 1us long so they are harmless)
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Old 14th February 2006, 05:47 AM   #29
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Ilimzn,

thanks for your detailed answer, as always an excellent teacher! Wasn't that your occupation btw?

So if I got you right you would due to the explanation given use a fixed cascoding voltage 5 and 20 volts for the cascoded BJT, right?

Cheers Michael
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Old 14th February 2006, 08:50 AM   #30
Eva is offline Eva  Spain
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Thiese are the open loop gain/phase plots that PSpice predicts:

Click the image to open in full size.


The O/L gain is flat up to 10Khz and the phase shift at that frequency is 90 degrees. Then, the gain is quickcly rolled-off at a 9db/oct slope thank to the pole plus pole/zero compensation. Closed loop gain is 30dB, so phase margin appears to be 60 degrees as the cursor shows, and all the audio band is kindly subject to 60dB of negative feedback. This was simulated in the crossover region, with 100mA bias, thus both gate drive cells working to compensate the very low gain of the MOSFETs at low currents.

It may look too optimistic, but the prototype is stable with these compensation networks. It doesn't ring when entering or coming out of clipping, being that a proof of good stability and phase margin.

p.s.: For all those subjectivists out there, it sounds just fine
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