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Old 4th September 2004, 06:56 PM   #11
andy_c is offline andy_c  United States
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Here's a simple plot of the characteristic curves as predicted by the OnSemi MJL3281A model. I tried to make them look as much like the data sheet as possible by having the same IC and VCE range and units per division. This required reducing the base currents in the simulation relative to the data sheet values due to the model having higher beta than the sample under test.

There's no modeling of the Early effect "bend" in IC/VCE, and the behavior in the region near saturation looks quite different and pessimistic compared to the data sheet info. The VCE step size was 0.1V.
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Old 4th September 2004, 08:33 PM   #12
Geoff is offline Geoff  United Kingdom
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Andy

Thanks for your input. I remember the previous thread where you found some problems with ft using ON-Semi models.

I have spent the last few hours investigating the current problem further, using the ON-Semi model for a 2N3055 and another model for the same device based on an old TI datasheet. The schematic I simulated is linked below. The input was a 1Vp 1kHz sine wave so the Vce of each output transistor did not drop below 10V (max about 35V). In other words, well clear of clipping, saturation etc.

The ON-Semi model displayed a current profile similar to that shown in jcx's original post ie a 'foldback'. The TI based model did not show this effect. However, increasing the load resistance (RL1) to 33R caused the 'foldback' to be increased when using the ON-Semi model and to appear with the TI-based model. I am now totally at a loss.

I have simulated both models for hFE/Ic, Vbe/Ic, Ic/Vce etc and nothing obvious is amiss. The only graph that did not seem to be totally realistic was the Vbe/Ibe for the ON-Semi model which gave higher Vbe values than I would have expected.

Geoff
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Old 4th September 2004, 10:07 PM   #13
andy_c is offline andy_c  United States
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Just for grins, here is the simulated DC beta of the MJL3281A at IC = 0.1A to IC = 10A with VCE = 1V to VCE = 20V in 1V steps.
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Old 5th September 2004, 02:38 AM   #14
andy_c is offline andy_c  United States
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I looked at this issue a bit more. First, it's helpful to calculate the output stage bias current. Referring to the schematic posted by jcx, if we assume the beta of Q2 is very large, and the betas of Q3 and Q4 are equal, it's easy to show that

Ic = beta * (I1 - I2) / 2

where Ic is the output stage collector current and beta is the (assumed equal) current gain of the output stage transistors. Now what is the maximum current that will be available to the base of Q3? This would occur if Q4 were cut off. If we assume the beta of Q2 is large, then the maximum base current drive available to Q3 is:

Ibase(Q3, max) = I1 - I2

To get more base drive to Q3 requires that Q4 conduct less. What's happening is that on the positive half-cycle of the output current, the base drive to Q3 is running out of steam, so the collector current of Q4 decreases disproportionately in order to get enough base drive to Q3. So the net change in load current on the positive half cycle is due much more to the reduction in current of Q4 than it is to the increase in currrent to Q3, since there's just not enough base drive to Q3 to make the contributions equal.

So one would think that we could just play with I1 and I2 to get more drive current and be done with it. If we try to increase the drive current of Q3, we must increase the difference in current I1 - I2. But if we increase this difference, we are no longer at our target output stage bias current. We could crank up both I1 and I2 such that their difference is constant in an attempt to give more base drive to Q3. But since the base drive available to Q3 is the difference between I1 and I2, it doesn't help a bit cranking them both up. If you use a higher beta output stage, you must decrease (I1 - I2) to keep the quiescent current constant. So you get proportionally less base drive. So we're stuck.
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Old 5th September 2004, 04:31 PM   #15
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Here's some more data. These are the simulated beta curves of the MJL3281A with the maximum VCE extended to 25 Volts to cover the quiescent case with the JLH circuit that jcx posted.

DC current in the output stage is 2.28A. From a DC analysis, and also the graph I've posted below, it can be seen that the DC beta of Q3 and Q4 is 163 at this IC and VCE = 25V. If you extend the analysis of jcx to show the base current of Q3 at its max collector current, it can be seen that beta at the max output current level is close to 100. So the beta at max current and 5 Volts VCE is 100 and the maximum base drive is 28 mA (I1 - I2). This gives only 2.8 A maximum output current of Q3. If its beta were constant at 163, you'd have 4.56A, a big difference.

The simulated data is definitely pessimistic compared to the MJL3281a data sheet. It can be seen from the data sheet that at 5V VCE and 20V VCE, beta increases with increasing current up to an IC of about 4A. The simulated beta does not reflect this.
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Old 5th September 2004, 08:59 PM   #16
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Hi lumanauw,

R.b sets the bias. Twin 390 ohm resistors balance (not current equalise) output half operation in the linear region and improves output transistor operating conditions when compared to the original 1969 JLH design.
TR5 is to pull TR4 base down in overload.

Hi Geoff and Andy,

Geoff your different simulation results are very interesting, as are Andy's investigations. Clearly there can be several different findings for the same circuit simulated by different individuals.
I have observed JLH output stages using an oscilloscope but never noticed that double hump as simulated by JCX.

A JLH amplifier does not simulate as well as many modern class-B designs, yet it often sounds better. It is the sound that counts, and this is what has made the JLH such an enduring design.

I have received an e-mail from diyAudio member John Lui who has constructed my amplifier and finds it very very good. He says that its crystal clear and detailed sound has surprised him with 'real' and 'solid' image placement. Photo attached - excellent work.
He says the 110V fans are running at 35V and are 'silent'.

Cheers ........ Graham.
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Old 6th September 2004, 06:44 PM   #17
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Hi All,

The double hump on the current curve appears to arise when the Forward Early Voltage is equal to or less than the peak to peak output voltage with this output stage which operates both output halves as common emitter current amplifying stages.
Waveform distortion remains low however.

When the Forward Early Voltage is reduced with complementary push-pull common collector class-A output stages a similar non-linearity effect can be discerned but does not current dip for equivalent voltage output.

Cheers ........ Graham.
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Old 6th September 2004, 07:05 PM   #18
andy_c is offline andy_c  United States
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I played around with this for a while and reached two conclusions.

1) The JLH design is very sensitive to output device beta vs Ic and Vce
2) The MJL3281a model has poor correlation to the data sheet regarding beta vs Ic and Vce.

So I set out to modify the model to get better correlation. The model turned out to have been done completely wrong. There's one odd thing with the data sheet though. The curves of beta vs Ic at Vce = 5V and Vce = 20V essentially fall on top of each other except at high currents. This implies the Early voltage is very large. Yet in computing the Early Voltage from the characteristic curves, a number smaller than the model value is obtained. I opted for the approach of getting data that matched the beta vs Ic and Vce at Vce = 5V and Vce = 20V. This approach gave a large Early Voltage value of 200 V. Here's the revised model.

.MODEL mjl3281a npn IS=6.5498e-11 BF=210 NF=1.00176 VAF=200 IKF=35 ISE=2.5e-11 NE=1.3 BR=4.98985 NR=1.09511 VAR=4.32026 IKR=4.37516 ISC=3.25e-13 NC=3.96875 RB=11.988 IRB=0.111742 RBM=0.102914 RE=0.00127227 RC=0.06 XTB=0.115253 XTI=1.03146 EG=1.11986 CJE=1e-07 VJE=0.4 MJE=0.450375 TF=7.04629e-10 XTF=1000 VTF=2.06045 ITF=41.8156 CJC=5e-10 VJC=0.4 MJC=0.85 XCJC=0.959922 FC=0.1 CJS=0 VJS=0.75 MJS=0.5 TR=1e-07 PTF=0 KF=0 AF=1

And here's the revised plots of beta vs Ic and Vce:
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Old 6th September 2004, 07:14 PM   #19
andy_c is offline andy_c  United States
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...and here are the revised waveforms. Note the much improved symmetry in the emitter currents over the signal swing.
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Old 6th September 2004, 08:28 PM   #20
Geoff is offline Geoff  United Kingdom
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Graham & Andy - thanks for your input.

After many hours of simulation and thought yesterday I eventually came to similar conclusions to yours (though perhaps not expressed in the correct technical terms :-). To avoid the Ic current 'dips', either at normal load impedance (with some models) or at higher load impedances (with others), the hFE/Ic graph needs to be as flat as possible from well below Iq to (ideally) 2xIq and the slope of the Ic/Vce graph (at Ic=Iq and Vce= Vsupply) should be near horizontal (in your terms, a high Early voltage).

I investigated 18 BJT models, 11 from ON-Semi and 7 from other sources. All of the ON-Semi models either displayed hFE/Ic slopes greater than the datasheet indicated or the Early voltage seemed incorrect (for example, the Ic/Vce graph for the MJ21194 was horizontal, and that for the MJ21196 not far off it).

As an aside, the datasheets for the MJ21194 and MJL21194 indicate that they are the same die in different packages yet the pspice models are completely different (and give different characteristics when simulated). How on earth is one to determine which is correct, if either, when they both give results that deviate from the datasheet?

Thanks for your revised model, Andy. I have tried this and now have no problems whatsoever with 'lumpy' current waveforms, even when the load impedance is raised to quite high levels. The only other model I have tried that achieves a similar effect is one for the MJ15003 (not from ON-Semi).

So where are we now? Is it safe to assume that the current anomalies are generated by inaccurate models and that reality is closer to the simulation results obtained using Andy's revised model? This is important when determining the optimum quiescent current for a particular load impedance. Simulation using 12 different models indicates that peak output current can be anything between 1.25 and 1.6 times the quiescent current (Andy's model gives 1.8 times, so comes much closer to true push-pull operation from the current phase-splitting action of the circuit).

Geoff
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