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Old 11th June 2002, 04:39 AM   #11
Dave is offline Dave  New Zealand
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I think a uC is overkill unless you were going design a sustained Platue bias system like the krell amps.
But here are my comments anyway,
You mentioned you'd get the uC to measure the gate voltages. I think it would make more sense to measure the voltage drop across the source resistors. That way there would be no calibration you just pre-program the uC with the voltage you want there.
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Old 11th June 2002, 11:05 AM   #12
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Default Re: Lateral V. Hex mosfets

Originally posted by HarryHaller

Seems that you answered your own question. At the risk of starting another riot, repeat after... me phase margin, phase margin, phase margin...... Good phase margin makes for stable amplifiers.

(Global) phase margin is always good but I doubt it is going to solve the problem Hugh describes. MOSFETs and fast, high-power bipolars can develop local oscillations if driven from a low impedance source.

A detailed analysis can be found in the 2000 edition of Tietze/Schenk: "Halbleiter-Schaltungstechnik". Unfortunately, the older editions, some of which were translated, do not contain this analysis in that much detail. You can have this effect even in the absence of any global feedback. In the end, it is still about phase margin, but only within a local, unintended loop.

I have experienced similar problems in my power amp that uses high speed Sanken bipolars as emitter followers. Under severe load conditions (i.e. 1 uF film from output to ground), the faster side (I think the PNP) would sometimes start to oscillate at >100 MHz at low amplitude, while the overall loop maintained stability.

One way of quenching the local oscillation was to increase base resistors, but turned out to slow down the output stage so that I would have had to roll off the voltage gain stage earlier to preserve phase margin under all load conditions. What worked perfectly well for me was to put a 2.5 mm ferrite bead on the base lead of each PNP output transistor. The amp is now stable with any kind of load (using only minimal inductive isolation on the output, three turns of 15 mm diameter) and I could keep the dominant pole at 25 kHz and the unity gain bandwidth at about 50 MHz.

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Old 11th June 2002, 02:39 PM   #13
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Exclamation local oscillations

"A gate resistor of around ...." Stopping mosfet from oscillating is not hard. An unity gain figure of 50MHz is asking for stability problems for a power amp. I believe the Ft for the Sanken output transistors is about 60MHz. This is about 10 or 20 times the bandwidth of a typical power amp.

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Old 11th June 2002, 03:56 PM   #14
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Wink Asking for trouble...

Well, I could have rolled the thing off earlier but then I wanted to obtain the highest bandwidth I possibly could. Having used lots of degeneration in the gain stages, getting the thing to be stable with a purely resistive input impedance and s 5 or 10 H output insulation coil was pretty easy. But I wanted to preserve treble damping factor (still am not sure whether that is needed), so I set myself the goal for the amp to be stable with all kinds of loads and only a 0.25 H coil. That was quite an effort, took me weeks to tweak the degeneration and the lead and lag compensation. The bode plot must look quite weird but what counts at the end of the day is the intercept angle at unity gain (there is a nice BB app note on that).

As a matter of fact, the local oscillation was quite helpful in adjusting the big loop. If it didn't break into a global oscillation after several seconds, the main loop was pretty stable. Another thing that helped in the end, all to my surprise was to use 10R base resistors between the input low pass filter and the diff pair input transistors, out of all places! Will post the circuit some day, once I succeed to find it...

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Old 11th June 2002, 06:01 PM   #15
mlloyd1 is offline mlloyd1  United States
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Default Re: Asking for trouble...

I've had to do this for a number of complimentary symmetrical power amp diff input stages I've built over the years. I know somebody will cringe, but at this point, I just throw in 10-100 ohms for any such input stage I build and call it done

Curious: are you using JFETs or bipolars? What currents are you operating at and how much degeneration are you using? I encountered this more often with bipolar inputs and high amounts of degeneration.

Originally posted by capslock
....Another thing that helped in the end, all to my surprise was to use 10R base resistors between the input low pass filter and the diff pair input transistors....

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Old 12th June 2002, 09:38 PM   #16
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uh oh, my reply was eaten by the computer crash (who ever pretended NT was stable???)!

I use SSM2210/2220 dual transistors (relaxed MAT02/03 in plastic case) at about 4 mA current, emitter degeneration is 27 R.

How come a complementary diff stage would be more susceptible than a single diff stage? For small AC signals they are very similar, after all.

Have you been able to figure out the differences between the Stoichino design and more conventional ones?


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