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Old 26th July 2004, 12:33 PM   #1
djdamix is offline djdamix  France
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Default DC offset on my design


I'm starting in audio amp design. My schema is attached. I' simulated my design and it seems to work (at the moment I'm not taking care of distortion ...). However with the simulation I get no offest (only 300mV) on the output, whereas on the PCB I get a 1,42V offset ...

Any help or comment are of course welcome !!
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Old 26th July 2004, 06:21 PM   #2
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Hi dAV!
...two comments from my side... just a first glance, not
simulated or rebuilt in reality:

R12 acts as a simple current source with around 4.3mA,
but Q5 only needs about 1.2mA (650mV /560 Ohms + some µA to drive Q7). So Q6 will run at about 3.1mA.
According to their different collector currents, Q6 will need much more
base current than Q5.

2. DC path for basis of Q5 is 10k, while DC path of Q6 is 56k.
Already with symmetric currents of Q5 and Q6, this would cause some
DC component (positive DC at output).

In combination with higher current of Q5 the output DC offset will come
even more higher, because Q5 which needs more base current is biased by a higher DC path.
My proposal:
1. Change R12 to 12k, this will balance the collector currents of Q5 and Q6.
2. Change R18 to 56k, this will balance the voltage drop in both DC bias paths.

In simulation, your DC offset should come close to zero, when you implent both.
Difference between reality has three classic reasons.
-Current gain of Q5 and Q6 might be lower than in simulation and with this unbalanced DC biasing will come worse than in simulation.
In well a balanced set up (as after changing 1 and 2), the current gain is not critical as long as both transistors have the same current gain.
- Unfortunately in reality your current gains of Q5 and Q6 might be slightly different ...
- Vbe of both transistors might be not perfectly matched.
- Temperature of both transistor might be different (quite probable if Q5 runs at 1.2mA while Q6 is at 3.1mA)

Good Luck
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Old 26th July 2004, 08:48 PM   #3
MikeB is offline MikeB  Germany
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Default Re: DC offset on my design

Originally posted by djdamix

However with the simulation I get no offest (only 300mV) on the output, whereas on the PCB I get a 1,42V offset ...

Hmm, 300 mv DC-offset is very much ! (0.3Volt, this gives already
visible movement of the speakers coil)
As chocoholic said, in simulation transistors of same type are
identical. In real world they are never.
Q5 and Q6 must be matched in real world for nearly identical
hfe's and vbe's. (hfe only if r18 and r19 identical)
R18 and R19 should be same size, this in combination with C8
and matched transistors plus balanced current result in very low DC.
In this case you can get below 1mv.
For testing you could replace r12 with a pot, and adjust it until
voltage measured between collectors of q5 and q6 is zero.
c8 seems too small to me, this should be above 100uf or you will
have no deep bass.
I did not simulate, but i think r12 should be ~10k. (try a 10k pot
+ 5k resistor)

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Old 26th July 2004, 10:04 PM   #4
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You should be able to eliminate C8 if you use a voltage divider to bias both transistors in the diff. amp., and a pot to adjust the DC to 0V. If you use a current source/current mirror in your diff. amp, the DC offset will be more stable, as long as the current through and power of each transistor is the same. In the real world, if a BJT gets warmer, its bias Vbe is less and it conducts more. The DC offset will tend to drift one way or the other, depending on which transistor in the diff. amp is dissapating more heat.

may want to include a small emitter resistor on the VAS stage.

10pf may be too small of miller feedback when considering the impeadence of the AC load line. Then again this will be determained by testing. Whatever sounds good.

You may also need some temp. compensation for the outputs, bias servo or such.

May also want to place zener diode from gate to source on the output FETs in order to protect them.

As your VAS moves along its AC load line so as more current will flow, (the positive half of signal) then Voltage on R22 will cause both FET's to be on at the same time!

Just some thoughts.
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Old 28th July 2004, 07:47 AM   #5
djdamix is offline djdamix  France
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Default Thanks a lot !

Thanks for all these advices, I've improved my design and the DC offset has been greatly reduced ( just with the first modifications, I get about 50 mV) now I'll work on the servo bias.

Have a nice day

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Old 28th July 2004, 09:45 AM   #6
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I reckon you're simply out by a factor of 2 in one of your calculations. Try R12 = 13k.
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Old 28th July 2004, 08:23 PM   #7
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Hi dAV!
...glad to hear that things are coming better now...

Have fun
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