Cascode VAS biasing ?

[sam9]

Consider a mirror image cascode VAS. The inner transistor is often (typically) biased by a zenner in the range 3.3V to 4.7V. Setting this up in LT Spice, I wanted to understand better what happens when you change the value. In the simulation, so long as the value is high enough to turn the transistor on (anything >~1.4V) the only effect is that the peak output gets closser to the rails the lower the value.

I don't believe things are as simple as this. What is the simulation not showing?

[sreten]

AFAIK it is basically that simple, though AFAIK a typical output
stage is not a good load for a cascode rendering it less than
really useful in the VAS stage.

If you cascode an input stage AFAIK it affects common mode range.

sreten.

[jcx]

junction capacitance is certainly increasing, even a little revese bias helps a lot vs 0 Vcb bias - but in principle spice should be able to do a good job with junction C

[sam9]

The cascode is contemplated with an MOSFET output stage which may satisfy the load issue. However, the Spice simulation uses BJTs for the simple reason that vitually every authoratative source breifly says that's a bad idea and then moves on.

That kind of thing sometimes sparks my curiosity. So I wanted to see what would happen without the trouble of constructing anything. Mysteriously, the simulation says the thing will function - appearently fairly well: no wierd HF noise or spikes, nothing odd at low signal or at or near clip. I've got an abondoned experiment in the garage that I maybe able to modify by air-wiring in a cascode VAS rather than the more standard one and see what it sounds like - maybe that will make things clearer.

[sreten]

But the point is to show some advantage of cascoding the VAS,
simply that it works is not the point, if the VAS has the usual
Miller Cdom then cascoding is pointless unless you change
Cdom connection to the cascode output, then what do you get ?

sreten.

[sam9]

"if the VAS has the usual
Miller Cdom then cascoding is pointless unless you change
Cdom connection to the cascode output, then what do you get ?"

That's what I did, actually. It never ocurred to me connect Cdom anywhere but the cascode output. What I get are FFT plots and .DISTO figures very similar to a Darlingto-esque beta enchaned arrangement. Both superior (in sim at least) to a single transistor.

[azira]

In a cascode with no degeneration, the CE is actually operating at unity gain and the CB operates at a gain of about -gmRc. The entire unit behaves just like a single CE amplifier. Except the advantage of the cascode is that since the CE amplifier has little gain, it's miller effect does not push the pole at the base to lower frequencies therefore better HF response. Putting a Cdom across this arrangement ends up killing what you worked for. But in terms of biasing, since the CE operates at unity gain, you can predict based on your input sensitivity where you need to bias the CB so that it remains on through the signal cycle.
--
Danny

[sreten]

Originally posted by sam9
"if the VAS has the usual
Miller Cdom then cascoding is pointless unless you change
Cdom connection to the cascode output, then what do you get ?"

That's what I did, actually. It never ocurred to me connect Cdom anywhere but the cascode output. What I get are FFT plots and .DISTO figures very similar to a Darlingto-esque beta enchaned arrangement. Both superior (in sim at least) to a single transistor.

I wasn't implying that you had not done this, just the major
advantage of cascode connection is not utilised. Dual types
will nearly always be better than a single transistor, but for
the VAS I'd suggest performance into low impedance loads
is the major criteria, and cascode does not compare well
with beta enhancement methods IMO.

sreten.

[sam9]

It was just because that a cascode is said to be inferior i to low impedance loads that I ran the simulation. To see what form the inferority would take. What puzzles me is, that in simulation, I can't see any indication of the inferiority. I'm not very interested championing one topology vs another. What I originally wanted (and expected) to see was some significant if slight indication in the sim behvioral difference between the two approaches. That I have not seen any only suggests to me that it is something spice can't capture or that I just don't know where to look.

The original question was kind of an offshoot as I was lazy at first and just plugged in the first reasonable zenner value that came to mind. When I looked closed it seemed that the best choice would just be lowest value that also kept the cascode transitor turned on. This just seemed suspiciously "too simple" to be true.