Take your own example: 60dB loop gain at 60KHz. This makes (for a single pole) a ULGF of 60MHz. That wouldn't be possible anywhere close for a power amp.
In a VFA, given a single pole non-compensated ULGF the only way to increase the loop gain at (say) 60KHz is to insert N poles and then N-1 zeroes to bring the phase back to the Bode stability condition. The larger N, the steeper the rolloff of the loop gain, but anything with N>3 is a practical nonsense, at least because of implementation and thermal stability issues. The only realistic example with N=3 I have ever seen is the Cherry NDFL topology.
Now show me a N=2 topology (TPC, TMC, whatever you fancy) with 60dB of loop gain at 60KHz and an ULGF of (an optimistic) 3-4MHz and I'll be fully in your VFA boat
. Or with N>=3 which is also unconditional stable.
Because of the x20 feedback resistor (R5/R6) over the emitter resistors (R36/R40), this is barely a real "CFA", but more like "a CFA topology in VFA mode" as described above. 1kohm barely loads the input node and therefore modifies the forward gain (through the transconductance of the input stage).
Because minor loop compensation of the shunt derived shunt applied variety can only be implemented around an inverting gain block (transimpedance stage). Nothing of the kind is to be found in the usual so-called "CFA".
There is no such thing as "small signal slew". There is only one definition for slew rate and power bandwidth, and it can be found in any good analog electronics textbook.
I suspect, however, that what you're alluding to is the distortion arising from the increased loading of the minor loop compensation network with increasing frequency on the transadmittance stage (the LTP) in a VFA. Some have called this "slewing induced distortion", but this is not a very descriptive term in my view-it will have to do, nevertheless.
I know the Alexander amp, which is really a voltage feedback amp. in all respects.
But, perhaps, I do not understand what you mean by "...you can use a VFA in "CFA mode"?
Ok, say 60dB @ 20KHz or 50dB @ 60KHz, is still a 20MHz ULGF, unattainable for a power VFA... 6dB extra loop gain for a two pole compensation, still to high for a power VFA.
Aw, Michael, you can do better than this
. Since I can't quote my textbooks here, it took me 20 seconds on Google, 5th paragraph.
The CFA has forward V amp path with V fb? The input is an EF, a voltage buffer. But the current mirrors, CM, convey current to the comp cap in the next stage, so this is a transadmittance function. The comp cap stage receives current as its input from the CM, then outputs a voltage, making it a transimpedance stage. The output stage is an EF, a voltage buffer. The forward path is V-V/TY/TZ/V-V, overall a voltage is inputted and a voltage is outputted.
The feedback from the output EF is realized by the current in Rf. You opined that the current In is merely the Vn value divides by the Thevenin impedance at the node. But this cannot be true if you examine it. The Thevenin Z at the - input is typically 3 to 5 ohms. In parallel w/ the feedback resistors, let's say 1.0 kohm for both, we get 500 ohm || 5 ohm, or 4.95 ohm. If the fb resistor pair is doubled to 2.0 kohm, the slew rate gets halved. Did the Thevenin Z get doubled to account for it? No, the Thevenin Z is 1.0 kohm || 5 ohm = 4.975 ohm, hardly different from before. Yet the slew rate and BW halved.
Your theory that the error is voltage and that the fedback current is merely the V divided by Thevenin Z holds water like a net. Take 2 identical CFA, 1 w/ 1.0 kohm fb pair, 1 w/ 2.0 kofm pair. The smaller values slew twice as fast, yet according to you, the error signal is the same for both, a voltage w/o regard to any resistance value. Clearly the resistance impacts the error signal because lower R values slew faster. The error signal cannot be a voltage because it's the same for both.
Likewise, Thevenin Z hardly changed from 1.0 to 2.0 kohm, yet sle rate & BW are a factor of 2 apart. You have no case at all.
You previously stated that the error signal is Vin-Vfb, then you now state that it is Vp-Vn. Which is it? Why does slew/BW change w/ Rfb if Vp-Vn is the error signal?
No "level shifting" at all here. Collector current value in 1st stage EF gets conveyed over to the comp cap in the TZ stage w/o any level shifting. Where are said level shifting components? This is totally off the wall.
Once again Michael, your explanations not only oppose OEM op amp makers, EE analog practitioners, uni profs, but they oppose your own pronouncements. You put forth a theory only to have it scrutinized and rebuked thoroughly, so you come up w/ another, etc. The error signal has been stated by you as Vp-Vn, Vin-Vfb, then you have added a level shifter to the current mirror which no OEM even mentioned.
Michale you beat all. You can't show anything w/ schematics, computations, etc. You are arm waving and nothing else. Give it up dude, the CFA may not be better for audio, I have already conceded to that, but it is indeed a current mode device. The CFA terminology is exactly correct, all arm waving to the contrary notwithstanding.
Claude
If you can't see that Vin-Vfb=Vp-Vn and that the current mirrors level shift signal from the input stage to the load then you're beyond help. I'll leave you to your handwaving.
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If you can't see that Vin-Vfb=Vp-Vn and that the current mirrors level shift signal from the input stage to the load then you're beyond help. I'll leave you to your handwaving.
No I don't see "level shifting". As far as "Vin-Vfb" goes, the voltage at the - input is not "feedback voltage", Vfb. I don't see it, nor the level shifting. Level shifting is displacing a signal by some amount. An example is using a FET gate driver designed for driving a grounded N-Fet, to drive a high side N-FET. The gate drive signal must be level shifted upward wrt ground.
How does a current mirror "level shift"? The value of current, dc plus signal, is conveyed to the comp cap w/o adding or subtracting anything. No level shifting at all.
Again, Vn is not a fb voltage. The Thevenin Z is so low at this node, the voltage at - input is dictated by the input driving the EF buffer. Vn is a buffered input voltage Vi. It differs only in voltage offset since a diamond buffer has 2 pair of bjt vs. 1 pair in a VFA. So I do not believe that Vn is a "feedback voltage Vfb". You assume that but cannot explain how the servo loop speed increases w/ lower Rfb. Clearly there is more going on than wghat you describe. Sketches and computations would help. Please show us how the servo loop gets perturbed when loading or input change, then show how the loop corrects the output. Include the error signal and computations. I did so in 2004-06 and in 7 yrs. you have never submitted a rebuttal. Thanks in advance for your help. BR.
Claude
Level shifting in the case of the complimentary common emitter "CFA" is transfering the AC changes in the input stage's collector current to the load without altering them in any way. This is the purpose of the current mirrors. Now, why can't a phd candidate see this?
If you cant see that a so-called "CFA" has a voltage divider draped across its output that delivers a fraction of the output voltage to the inverting input of your so-called "CFA", then you're really beyond help.
At least Professor Leach and Professor Cherry were able to see this most elementary of facts.
Leach's analysis is just wrong, the forward path has no dependence on the feedback network. Cherry is just narrowly interested in audio, academic with no commercial potential. Let's avoid the yellow snow while we're at it.
I also feel I have wrapped my head around this constant bandwidth thing.
Imagine a CFA with feedback resistor Rf and resistor to ground Rg. The loop gain/error current runs through Rf and the inv input node; it does not run through Rg because Rg is in parallel with the inv node input Z which is at least an order of magnitude smaller than Rg.
So the loop gain depends only on the various paths in the chip and Rf, so for a given Rf the BW and distortion characteristics are fixed, independent of Rg!
But, you can still modify the voltage gain of the whole circuit by modifying Rg.
So this gives you a circuit where you can modify the voltage gain with constant BW and linearity!
Some call this an advantage, but Mike has a point when he sees it as a disadvantage: in a VFA, when you decrease the voltage gain you get wider BW and lower distortion. This doesn't happen with a CFA.
jan
Imagine a CFA with feedback resistor Rf and resistor to ground Rg. The loop gain/error current runs through Rf and the inv input node; it does not run through Rg because Rg is in parallel with the inv node input Z which is at least an order of magnitude smaller than Rg.
So the loop gain depends only on the various paths in the chip and Rf, so for a given Rf the BW and distortion characteristics are fixed, independent of Rg!
But, you can still modify the voltage gain of the whole circuit by modifying Rg.
So this gives you a circuit where you can modify the voltage gain with constant BW and linearity!
Some call this an advantage, but Mike has a point when he sees it as a disadvantage: in a VFA, when you decrease the voltage gain you get wider BW and lower distortion. This doesn't happen with a CFA.
jan
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