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Old 2nd May 2004, 07:23 PM   #1
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Default Question about output stage used in open loop

Hi there,

I have a problem with designing a power amplifier which does not use multistage feedback. While I was able to desing and build voltage amplifiers without multistage feedback I just couldn't answer the question of the last stage.

First, I tried to learn why the last stage is nested in the feedback loop most of the times and I came to the following conclusions:
1. Without the feedback the non linear natur of the (power) BJTs would lead to a distorted signal.
2. The output impedance of the amplifier (or should I say "resistance"?) is decreased by using negative feedback. This is - of course - essential to reach good damping.

According to my knowledge the first issue can be handled.

The 2. point is where my knowledge seems to give up. I read many times that connecting several power BJTs in parallel should solve this problem, but I do not see how this practise is capable to deliver the goods.

I understood that the output resistance of the BJT should be calculated by divining the thermal voltage (generally 26mV is used by such calculations) with the bias current. (Of course I am talking here about an emitter follower configuration.) If the latter is about 200mA then the result is 130 mOhms. If we connect an other emitter follower with 200mA bias current then that will have 130 mOhms output resistance in itself too and becasue of Ohm's law the two together would have half of the output resistance, which is 65 mOhms. As I see it is because of the higher overall bias voltage and if we apply 400mA to a single emitter follower we will have the same result.

What it isn't clear for me:
- Can the equation I used above applied to calculate both AC output impedance and DC resistance?
- Which of the two parameters (AC and DC output impedance/resistance) is really important?
- How much bias current shall be used to drive real life speakers? (In other words: how much current is enough?) The queastion is not about the power handling capacity now. How much bias current is needed to achive low enough output resistance.
- I read in some articles that by applying parallel output transistors or class A (wich means using higher bias current as I see) would lead to decreased distorsion. I can not see how this is possible. (I am talking here about simple emitter followers, no CFP.)
- Is there a recommendation regarding how much the damping factor should be?

Thanks for any help.

bt
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Old 2nd May 2004, 07:57 PM   #2
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If there's some way you can get your hands on a copy of Doublas Self's book on audio power amplifier design, you can get a wealth of information on conventional biopolar solid state design. He also does some analysis of output stage configurations. The Emitter follower triple T circuit can be quite linear open loop, especially when using the extended beta range transistors like those available from Toshiba and On Semiconductor. Paralleling transistor increases the SOA and ouptut current capability, and lowers the net output impedance.

Other approaches like the CFP output stage measure well under some conditions, but may not be as robust with reactive loads, and usually have issues about the turn-off speed for the power devices- due to low turn-off drive current available. For this reason driving them at high frequencies (20 kHz and above) at high power levels can be risky...

I did a high power CFP stage a few years back with Magnetek MSOFETs that worked quite well, but the driver was a "full size" MOSFET, and the turn-off resistance for the driven banks of MOSFETs was quite low, so it was more the exception that goes against the rule due to design innovation, rather than the typical bipolar implementation.

And if you want to do an amplifier without feedback loops, technically speaking, using a CFP pair is cheating, as there is a two stage loop contained therein.

The emitter follower triple isn't glamorous, but it gets the job done... with good design it's possible to get distortion numbers in the output stage under 0.005% open loop... isn't that low enough?

~Jon
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Old 3rd May 2004, 12:05 AM   #3
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Quote:
Originally posted by JonMarsh

... with good design it's possible to get distortion numbers in the output stage under 0.005% open loop... isn't that low enough?

~Jon
Low enough yes, but how do you achieve it without feeback?
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Old 3rd May 2004, 06:28 AM   #4
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JonMarsh,

I am aware of the drawbacks of the CFP and I don't plan to use that configuration

I haven't read the book from Self, maybe it's time to get one. Although I have to mention that most books do not speak about open loop solid state designs, but maybe this one is an exception...
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Old 3rd May 2004, 07:01 AM   #5
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Default You got down to 0.005%!

Only got mine down to 0.01%. But then I ran out of room on the heat sink.

Yeah......if I had room for a few more.

I used to build amps with CFP outputs. The open-loop output versions sounded better, and did not have problems oscillating in the 2-5 MHz range.

Jocko
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Old 3rd May 2004, 08:00 AM   #6
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Quote:
Originally posted by JonMarsh
[snip]The emitter follower triple isn't glamorous, but it gets the job done... with good design it's possible to get distortion numbers in the output stage under 0.005% open loop... isn't that low enough?

~Jon
Hello Jon,


0.005% open loop? Wow, that's impressive. Care to elaborate on this?

Jan Didden
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Old 3rd May 2004, 08:05 AM   #7
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Jan, a diamond buffer (open-loop) can also produce low distortion. When I measured my buffer with my soundcard it was less than 0.008% (the soundcard itself)
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Old 3rd May 2004, 08:35 AM   #8
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Yeah, sure, but this is a power output stage, I guess with load! That's a different kettle of fish.

Jan Didden
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Old 3rd May 2004, 10:59 AM   #9
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Good questions.
You need an output Z of 0.2ohms for good performance.
Assuming the voltage driver stage has very low Z, the output Z will be determined by the transconductance of the output device(s). Forget the maths. Look at the curves in the datasheet for the power transistors. From these you can draw the output Z vs Ic and see how much Ic is needed to achieve 0.2ohms or less and you can then see if there is an optimum Ic for minimizing Gm vs Ic.

You won't be able to estimate the imaginary part of the Z without great difficulty. So don't try. Just use low capacitance devices. Don't think of dc and ac separately - both are important.

I agree with you questions about paralleling devices. It doesn't really help in any way except to allow devices to be operated on a more linear part of the Gm curve or to distribute power. I do not recommend paralleling devices unless you have compelling reasons to do so.
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Old 3rd May 2004, 01:49 PM   #10
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Default The caps.

Peranders,

The caps are wearing mini skirts !
Did they come that way or did you cut away the rest of the plastic sleeve? If so ,why ?

Ashok.
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