samod's mosfet amp

[samod]

Hi everyone!
I will overpunch the new scheme.
In new amplifier has used several ideas thereof forum.
Shift to the right if there is blunders.

I am a beginner amateur , me a great deal not known.
Shall be grateful for responses.
To message join; archive with document from Micro-Cap 7.1.0
Prompt , cost(stand)s try this collect?
Thank you for attention.

[millwood]

Originally posted by samod
Hi everyone!
I will overpunch the new scheme.
In new amplifier has used several ideas thereof forum.

it looks good. a few questions:

a) do you really need two ccs for the VAS?
b) Q7 and Q10 idles at about 10ma. so the voltage drop over R12 is 200mv. Is that enough to open up those two mosfets?
c) it is probably OK to use a resistor to set bias for the two mosfets. But a Vbe multiplier would be more versatile.
d) you may want to use two source resistors here. They aren't required for the type of the mosfets you use but I always use source resistors to help stabilize bias and provide versatility: you can always jump them with a straight wire.

[demons_wing]

hi

thats a neat design..i am inexperienced too (very in fact!!) so what i say might be garbage, BUT i dont understand why the degeneration resistors for the diff pair are different??...and also, is R5 necessary?...

the design is simple i think..not a huge signal path which is good as far s i understand...maybe someone can enlighten me? it would be much appreciated...excellent attempt though, better than i could have done

[millwood]

Originally posted by demons_wing
BUT i dont understand why the degeneration resistors for the diff pair are different??...

he was probably playing around with their values to get an acceptable offset.

[samod]

I write using translator .
He not all correct translates.
Answer that questions which realized:
I have enclosed the documents , which explain the choice an element.
One drawing was will take from this forum.
I have considered such scheme justified , distortion less...
( this about modes.Q7 Q10)

The Second drawing emulation dynamic DC Resistors : R18+R19 , R12 possible not constant!
The Choice output transistor is conditioned by their warm-up dependency.
All while has tested on emulator. Shall Tomorrow try to collect , can this and in vain spent time.
Shall try.
-------------------------------------


Can Not enclose again files , does not allow the forum.
See beside me...
http://www.kievsat.com/phpBB/download.php?id=970

[fab]

Originally posted by demons_wing
hi

...BUT i dont understand why the degeneration resistors for the diff pair are different??...and also, is R5 necessary?...

the design is simple i think..not a huge signal path which is good as far s i understand...maybe someone can enlighten me? it would be much appreciated...excellent attempt though, better than i could have done

For the degeneration resistors, yes probably for DC offset cancellation. But the main problem is that the DC input impedance at J0 FET is 100k and the DC input impedance at J1 FET is 22K. This creates a high DC imbalance. Normally, the same value should be used for R9 and R13 to minimize the DC offset. If the FET input pair is not well matched then even similar input impedances may still require a DC adjustment but for that use a small trimpot (200 ohms or more for example) because the actual degeneration resistors chosen value will only work in this particular project.

I do not see the purpose of R5 since Q8 is able to sustain a lot higher voltage and power than that.

C3 is probaly a little low to avoid a relatively high phase shift at 20 Hz.

I suppose C8 is used for test purpose only of response to square wave in capacitive load.

What is the resulting mosfet bias current with R12 = 20?

[peranders]

Originally posted by samod
I write using translator .
He not all correct translates.

If you use software, try to write by yourself. I convinced that you can do it better. Sometimes I use french -> english and I don't understand a thing. when I use english -> german they at me. The same thing.

[samod]

Greetings to all!
I pleased with result of the work.
This amplifier on a model payment today has soldered.
It has earned! It was necessary to pick up R12, it became 100 ohm. Resistor R13 has put 100 k, R7-2,7 k. Transistor Q10 has replaced on 2SB649, Q7 - 2SD669 / a Feed +-42Â. was not possible to compensate completely drift 0, R18+R19, the tuning resistor, there were 0,014 V.
Likely it is necessary to pick up an entrance pair (I did not select). How to check up key parameters? Can there are programs for it?
Thanks.

[fab]

FET inputs pair are hard to keep a constant DC offset since it usually drifts with small internal temperature changes. Matching FET inputs may not be necessary since a DC offset of 14 mv is not so bad considering the use of FET in input pair. For R18+R19, have you used a trim potentiometer? I would try to match FET input transistors only if R18 is very different from R19. Matching FET inputs pair (in DC) could be probably done trying to match IDSS currents for each FET.

[samod]

Thanks for the response.
Instead of R18+R19 I used an accurate potentiometer 200 ohm. At equality R18=R19, displacement 0 = 0,128 V.
To adjust it is necessary in the end.
200 ohm + 0 ohm turns out...
Can it is necessary to pick up R6?
But then current JFET will change...
While I think.