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Old 17th October 2015, 09:51 PM   #1
Waly is offline Waly  Burkina Faso
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Default Blameless VFA with high ULGF and high open loop bandwidth

Don't want to create any kind of debate, this is just to show Dadod how easy it is to create a (more or less) Blameless VFA with very similar performances as his much praised CFA baby.

It's before any optimization (regarding the 2 pole compensation, in connection with the bias and the phase correction caps), which are left to the reader discretion. Schematic, results and models are attached.

This first shot shows a 6MHz ULGF and 78dB loop gain @ 20KHz. Stability is rock solid with 88 degrees phase margin and 10dB gain margin. If I recall correctly, Dadod's CFA has (also simulated) about 5MHz ULGF and 80dB loop gain @ 20KHz, certainly in the 10% range of optimization, not to mention the large gap in complexity. Slew rate is of course much lower that in a CFA, but at ~50V/uS (no overshoot) is still far from what is required to avoid PIM distortions (at 120W/8ohm output).
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File Type: png blameless_schematic.png (49.9 KB, 345 views)
File Type: png blameless_gp.png (44.2 KB, 341 views)
Attached Files
File Type: txt blameless_models.txt (3.7 KB, 25 views)

Last edited by Waly; 17th October 2015 at 09:57 PM.
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Old 17th October 2015, 10:29 PM   #2
bimo is offline bimo  Indonesia
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Quote:
Originally Posted by Waly View Post
Don't want to create any kind of debate, this is just to show Dadod how easy it is to create a (more or less) Blameless VFA with very similar performances as his much praised CFA baby.

It's before any optimization (regarding the 2 pole compensation, in connection with the bias and the phase correction caps), which are left to the reader discretion. Schematic, results and models are attached.

This first shot shows a 6MHz ULGF and 78dB loop gain @ 20KHz. Stability is rock solid with 88 degrees phase margin and 10dB gain margin. If I recall correctly, Dadod's CFA has (also simulated) about 5MHz ULGF and 80dB loop gain @ 20KHz, certainly in the 10% range of optimization, not to mention the large gap in complexity. Slew rate is of course much lower that in a CFA, but at ~50V/uS (no overshoot) is still far from what is required to avoid PIM distortions (at 120W/8ohm output).
Slew rate 50V/uS is too little. Mine with PSU +-45VDC have 90V/uS (measured), a Blameless with TMC compensation. I think you can do it better.
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Old 17th October 2015, 10:59 PM   #3
Waly is offline Waly  Burkina Faso
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Originally Posted by bimo View Post
Slew rate 50V/uS is too little.
Here it goes. Yes, it can be likely upped to 100V/uS by at least two methods (or, at best, their combination, thereof), without much impact on the stability or loop gain. Such useless gizmos are left to the interested reader. I personally don't care of anything exceeding 1V/uS per peak output volt.

Sorry, those believing they can hear the difference between 50V/uS and 100V/uS are, by myself, routed to /dev/null.
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Old 18th October 2015, 05:09 AM   #4
dadod is offline dadod  Croatia
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Quote:
Originally Posted by Waly View Post
Don't want to create any kind of debate, this is just to show Dadod how easy it is to create a (more or less) Blameless VFA with very similar performances as his much praised CFA baby.

It's before any optimization (regarding the 2 pole compensation, in connection with the bias and the phase correction caps), which are left to the reader discretion. Schematic, results and models are attached.

This first shot shows a 6MHz ULGF and 78dB loop gain @ 20KHz. Stability is rock solid with 88 degrees phase margin and 10dB gain margin. If I recall correctly, Dadod's CFA has (also simulated) about 5MHz ULGF and 80dB loop gain @ 20KHz, certainly in the 10% range of optimization, not to mention the large gap in complexity. Slew rate is of course much lower that in a CFA, but at ~50V/uS (no overshoot) is still far from what is required to avoid PIM distortions (at 120W/8ohm output).
Is that cap (Cvas) realy 1 F?
This is just basic simulation, I need to put it in LTspice to check it, but for real amp is still much to go.
Input cap of 100 uF and you should use electrolytic cap. The Gain margin of 10 dB is not so good and probably stability is not rock solid . For me to use so small gate resistors is suspicious, but I don't know those mosfets. In mine VFA amps I never used mosfet OPS, could be that the trick is there, I will check.
My amp is simulated but it was built too.
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Old 18th October 2015, 06:21 AM   #5
bimo is offline bimo  Indonesia
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Quote:
Originally Posted by Waly View Post
Here it goes. Yes, it can be likely upped to 100V/uS by at least two methods (or, at best, their combination, thereof), without much impact on the stability or loop gain. Such useless gizmos are left to the interested reader. I personally don't care of anything exceeding 1V/uS per peak output volt.

Sorry, those believing they can hear the difference between 50V/uS and 100V/uS are, by myself, routed to /dev/null.
I was tried several amp and made those amp have different slew rate and then listen. If you can not hear the difference is OK
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Old 18th October 2015, 07:26 AM   #6
dadod is offline dadod  Croatia
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Here is my quick simulation and it does not look promising, GM to low and LG plot with a peak at 30 MHz.
I used Cordell's model and low base resistors as in your sch. With 150R the plot looks better but PH is to low.
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Old 18th October 2015, 07:45 AM   #7
pwan is offline pwan  United Kingdom
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Any reason on using 2SA1381 for LTP, esp. it's relatively low hfe while running at high idle current?

PS: IMHO, I'd use lower voltage for Q312 e.g. BC549, 559, 560 since it's higher hfe.
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Old 18th October 2015, 08:44 AM   #8
dadod is offline dadod  Croatia
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Originally Posted by pwan View Post
Any reason on using 2SA1381 for LTP, esp. it's relatively low hfe while running at high idle current?

PS: IMHO, I'd use lower voltage for Q312 e.g. BC549, 559, 560 since it's higher hfe.
I hope Waly will answer that, I just use the same as in his schematic.
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Old 18th October 2015, 08:44 AM   #9
Waly is offline Waly  Burkina Faso
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Quote:
Originally Posted by dadod View Post
Is that cap (Cvas) realy 1 F?
This is just basic simulation, I need to put it in LTspice to check it, but for real amp is still much to go.
1f=1femto

Absolutely, this is basic simulation, this is not something to be built right away. You asked for a proof of concept, you got it. So quibbling about details is irrelevant at this point. You are free to further experiment and optimize the behaviour, the important point is that a very basic Lin topology can meet the much praised CFA loop gain performances.

Mr. Cordell models are in general very basic, and only one step away from the manufacturers crap. The attached models are fixing a few important issues, like the Ft-Ic dependency (for the 1381/3503) and the lack of sub threshold model for the basic mosfet models.

1381/3503 have very high Early voltage so even with low beta the IPS transconductance is very high (the devices output impedance doesn't load much the IPS). Of course, a hybrid solution of a high beta device cascoded by 1381 for high Early is possible. Again, this was a quick and dirty proof of concept.
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Old 18th October 2015, 09:30 AM   #10
dadod is offline dadod  Croatia
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Quote:
Originally Posted by Waly View Post
1f=1femto

Absolutely, this is basic simulation, this is not something to be built right away. You asked for a proof of concept, you got it. So quibbling about details is irrelevant at this point. You are free to further experiment and optimize the behaviour, the important point is that a very basic Lin topology can meet the much praised CFA loop gain performances.

Mr. Cordell models are in general very basic, and only one step away from the manufacturers crap. The attached models are fixing a few important issues, like the Ft-Ic dependency (for the 1381/3503) and the lack of sub threshold model for the basic mosfet models.

1381/3503 have very high Early voltage so even with low beta the IPS transconductance is very high (the devices output impedance doesn't load much the IPS). Of course, a hybrid solution of a high beta device cascoded by 1381 for high Early is possible. Again, this was a quick and dirty proof of concept.
This is proof of nothing, I simulated with similar result a few years ago a VFA with TMC(blameless- 73 dB LG at 20kHz) and with similar low Gain Margin. I built a TT VFA amp ThermalTrak+TMC amp.
I don't say that VFA can't do many things as CFA, but not all, SR and very tolerant compensation behavior is the strong point for CFA.
Cordell's mosfet models use additional parameter ksubthres:

* VDMOS ksubthres models
*
* IRFP240Ckst VDMOS copyright Cordell Audio December 20, 2014
.model irfp240Ckst VDMOS(nchan Vto=3.0 Kp=4.8 Lambda=0.0032 Rs=0.01 Rd=0.1 Rds=1e7 Cgdmax=2600p Cgdmin=10p a=0.35
+Cgs=1250p Cjo=3000p m=0.75 VJ=2.5 IS=4.0E-06 N=2.4 ksubthres=190m)
*

Your mosfet models did not run in LTspice.

Attached LG plot of my TT VFA TMC. I built a bit simpler compensation variant as this was quite sensitive to components tolerance.
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