L10 amplifier need VI limiter

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Download Michael Kiwanuka's article on VI limiters from Bonsai's site. His Fig 1 shows the trigger transistor feed at the driver base, after the resistor Rs.
I've created macro's for most of the VI arrangements he describes, using his analysis method. MK's preference appears to be Fig 28, the zener arrangement I offered above. For 63V, however, a triple slope might be desirable.
 
Guys ...can i really get some help here ?

Been spending almost 3 days on MK paper and my neither my English is enough to understand it properly nor my math is to come up with usable calculation or to come up with a usable schematic since i cannot really understand why schematic B next to schematic A .

My output will be 21193-4 , my rails are 65+65 at absolutely no load conditions ( DC) and my emitter resistors are 0.22

thanks
Sakis
 
Further more
rough calculation say that 3 pairs on 65 stiff rails ( 600W trafo ) is a bit edgy and expected to be pushed if load is 4 ohm
Given as a fact that i have huge sink, twin tunnel ventilators, 2 speed forced cooling i expect that i will not face temp issues

So limiter has to be calculated in a way that will start to kick in bit early in order to protect against high current in case of 4 OHM overdrive

What is left will be an 8 ohm amplifier with good headroom up to a specific point of power while distortion and dynamic limiting is expected after some point of power whic is a situation that i am absolutely ok with ...

Kind regards
sakis
 
A similar two slope arrangement as before, with Tc = 50degC and Vbe = 0.6v as described by Kiwanuka. Note that the Vbe of the sense transistor defines the activation point, and any reduction will adversely impact on the limiter action.
 

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Thank you very much i will study that and see .

One thing that i cannot understand
do you suggest that limiter transistors should sense temperature ?
Do you suggest that limiter transistors should kept cold and away of the heatsink ?

In my arrangement ( as we speak at design level ) the limiter transistors will exist in the ventilation path and expected to remain cool at all times and exist no where near high temperatures .

The way i ve done it is with electronic thermostat activated about 50-52 degrees then twin vents inside a canal will ventilate the heat away while the boards will be outside the area and heat produced by the output .

Limiter transistors are expected to be in room temperature or just a bit higher which means in our country something between 20-50 degrees

Kind regards
Sakis
 
The VI limiter I posted ideally triggers at 0.6V. All other things being equal, if VbeQ2 is lower, the limiting action occurs earlier; e.g. for Vbe = 0.5V, there is a downward translation of the limiter by about 1.8A. Thus it will activate too early. To restore it, R2 needs to be ≈120Ω. If Vbe = 0.4V, R2 ≈ 91Ω. Thus your choice of Q2 and its Vbe determines the effectiveness of the protection.
There is a school of thought that suggests* that Q2 be thermally coupled to the output device so that the decreasing OP-SOA due to temperature rise be tracked to some extent by the Q2 negative temp coefficient. Calculation shows that this can, indeed, be theoretically viable. However, I’d prefer to keep Q2 at some reasonably constant temperature to fix the VI limiter (e.g. by mounting them against the driver heatsink), and prevent its violation by maintaining the maximum OP derated SOA outside the VI boundary.
As they say, YMMV

*AES 5695

and one other thing
Your model is based on a specific limiter transistor and his pair ?

No.
 
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