I have been looking around in how to optimize CFP as OPS stage. I don't mean how it works, it's simple. What I am looking for is how to optimize the value of the emitter and collector resistors of the driver transistor and the emitter resistor of the power transistor. What current is optimal in the driver transistor compare to the power transistor?(again, value of the emitter and collector resistors).
I want to know why Self claimed that you can run lower bias current on CFP than EF(p277 to 279). Also why Self claimed paralleling CFP actually hurt in the crossover distortion(page 241)
I want to read about how to tame the oscillation of CFP stage.
All the articles I've seen are either basic explanation or just give the schematic. I want to know the details on how to design it.
Thanks
I want to know why Self claimed that you can run lower bias current on CFP than EF(p277 to 279). Also why Self claimed paralleling CFP actually hurt in the crossover distortion(page 241)
I want to read about how to tame the oscillation of CFP stage.
All the articles I've seen are either basic explanation or just give the schematic. I want to know the details on how to design it.
Thanks
Hi,
Optimum bias current for CFP is simply much lower than EF.
As Self explains bias voltage is what really matters, and
the current varies with the emitter resistor values.
rgds, sreten.
Optimum bias current for CFP is simply much lower than EF.
As Self explains bias voltage is what really matters, and
the current varies with the emitter resistor values.
rgds, sreten.
That's the very thing I don't like Self's book. If you look at Table 10.2 and 10.3 in page 278, He GAVE you his optimal Vq. My question is Why? I absolutely understand the EF in Table 10.2 that the EF follow Oliver's optimization to make the change of output impedance down to minimum during crossover. That is explained nicely in Cordell's book. I read through the chapter over and over. Self gave assertion without presenting the reasoning a lot of times. I have no idea the reason why the crossover distortion is minimize with low bias current in CFP. I don't like to fly blind.
I hate to say, I read chapter 9 and 10 of Self's book, I don't like the book. I found him confusing. He like to talk about both CFP and EF output stages. BUT he does not label his explanation in quite a few places. You have to stop and guess which one he is talking.
This is worst on the middle left column of page 279. "As Re is varied, Vq varies by only 29%, while Iq varies by 365%...............As Re is varied, Vq varies by 230% while Iq varies by 85%......"
He is talking about Table 10.2 and 10.3 between EF and CFP. But he NEVER ones identify the first sentence refers to 10.2 and the second sentence refers to 10.3. I actually had to pull out the calculator to calculate the % variation of the two to identify what he is talking about. I am actually quite angry spending the money to buy this book.
Then he claimed Class B is much lower distortion thatn Class AB. BUT is optimized current for his Class B with EF using Re=0.1ohm is 215mA!!! In what world you run 215mA bias current in Class B? In what world the two half of the circuit conduct only 50% with 215mA bias current? In my book, that is strong class AB with pure class A at lowing 10W output!!!
All the talks about distortion in chapter 9 and 10 is at very high power level. In what world you run your audiophile amp at that level?
Sorry about the rant. I am actually quite angry with the book because I bought it, so I should read it.
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Hi Alan,
Rod Elliott did a good research on CFP, comparing it to Darlington pair.
>Compound Pair Vs. Darlington Pair<
Hope this helps.
Rod Elliott did a good research on CFP, comparing it to Darlington pair.
>Compound Pair Vs. Darlington Pair<
Hope this helps.
Hi,
Selfs class B is in my book aB, and yes you need about 200mA with
EF 0.1R emitter resistors, which gives nothing like real EF class AB.
Sadly you do need to know some of your stuff to decipher Self.
10W pure class A needs a lot more standing current than 200mA.
I quite agree low distortion near maximum power is meaningless.
For Self you have to read between the (biased) lines.
There is a lot of useful information nevermind his interpretation.
Over the years his re-editions, pruning and additions can be
and are inconsistent, its a fallible world we all suffer from.
rgds, sreten.
Selfs class B is in my book aB, and yes you need about 200mA with
EF 0.1R emitter resistors, which gives nothing like real EF class AB.
Sadly you do need to know some of your stuff to decipher Self.
10W pure class A needs a lot more standing current than 200mA.
I quite agree low distortion near maximum power is meaningless.
For Self you have to read between the (biased) lines.
There is a lot of useful information nevermind his interpretation.
Over the years his re-editions, pruning and additions can be
and are inconsistent, its a fallible world we all suffer from.
rgds, sreten.
I mistaken by thinking my design of 5 stages of 200mA each to get 2A of peak current to get about 8W. My bad.
From reading the two chapters, to me, this is a book on distortion of power amp, not really "Audio power amp design". I don't need him to explain how CFP works. BUT if he is so concentrate on distortion, then he need to explain why CFP is lower distortion instead of just give the numbers and have people trust that!!! Of cause I expect to learn something out of the book. If I have to learn everything else, I don't think I need his book to summarize it.
I got spoiled by Cordell's book. Cordell always give enough info for you to pick it up and run with it. Maybe because both Cordell and me had been an analog IC designer before, he understand his terminology and trend of thinking much better. Too bad Cordell did not go deeper into CFP.
I finished reading the article. Now I see why CFP has better thermal stability because he expect the driver transistor to be NOT on the main heat sink, but have a separate heat sink with the pre-driver and the bias generator.
I kind of understand why it has lower distortion because the gain is closer to unity than 2EF. This implies the output impedance is lower than 2EF, so crossover distortion should be less.
BUT it still does not explain why Self claimed that the crossover width of CFP is much narrower than 2EF. That will generate higher harmonics than 2EF.
Also, why Self claimed the crossover distortion get worst with more pairs in parallel while 2EF gets better with more pairs in parallel.
Also what is the optimal current ratio between the driver and the power transistor.
Yes, this is a good article that explain some of my questions.
Thanks
Allow me to suggest that you may have a Eureka Moment or two, if you watch a Sziklai pair output stage as it clips and also as it recovers from clipping when driving a reactive load. This exercise quite possibly might alter your opinion about the optimum values of the resistors (ratios actually) in the stage.
I just did a simulation using Table 10.3 with Re=0.1ohm and Iq=15mA. Attached is the asc file and FFT at 20KHz run for 5mS and 0.0005uS step. In what world is this low distortion? I had done many simulation in 3EF and 4pairs of CFP at 200mA per pair and get much better result I posted in another thread!!!
Hi,
Self doesn't claim the CFP increases in distortion with more parallel pairs,
unless you have an edition I haven't read, he claims quite the opposite.
Distortion reduces when increasing load impedance and / or paralleling.
As ever, Iq is irrelevant, Vq is what matters the most, for optimum aB.
rgds, sreten.
Self doesn't claim the CFP increases in distortion with more parallel pairs,
unless you have an edition I haven't read, he claims quite the opposite.
Distortion reduces when increasing load impedance and / or paralleling.
As ever, Iq is irrelevant, Vq is what matters the most, for optimum aB.
rgds, sreten.
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In Table 9.3 page 241 of the 6th edition. It gives the Peak-dip gain difference. That is where the crossover distortion comes from.....from the change of output impedance that form a divider with the load.
I still don't know why for CFP, but for EF, Vq is implied by Iq as explained ( and I agree) by Cordell. From Oliver's paper, the Re should equal to r'e (page 49 of Cordell) so the output impedance of the OPS is the same when both sides are on(Class A) vs only one side is on(Class B). That turn out the optimal resistor value of Re would give 26mV of Vq per side and about 52mV. This of cause is the first pass approximation as parasitic resistance needs to be accounted for. BUT this originated from Iq....that Self failed to mention.
What I really want is to have a crystal clear explanation why CFP
1) has more crossover distortion when parallel up to 6 pairs.
2) Why CFP needs to run at lower bias current ( which my simulation does not turn out).
3) What is the formula to show the output impedance is lower than EF to get less of a voltage divider effect.
4) How do you optimize the current ratio between the driver and the output transistor.
5) Why CFP has a much narrower spread at the crossover.(page 278 table 10.2 and 10.3)
None is answered in Self's book. You would think as a big proponent of CFP, he would at least care enough to educate people.
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You are relying on just 2 texts levelled at non-academics and your own Spice simulations for in-depth technical research. Surely, you need to look deeper and wider, starting with their references, to satisfy your interest in research level information.
As you are querying the work of just the 2 authors, why not approach them directly in their threads here or by PM etc?
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I don't think D Self can be reached as he doesn't come on hardly. This is outside Cordell's book, he did not claim any of these. These two are supposed to be the best......although I can only agree to Cordell's book. I studied the IC design book of Grey and Meyer, I don't think they cover this that I remember.
But more importantly, people here design with CFP, nobody can answer these questions? I don't think these are particularly deep. Basically it's a two CE stage with the collector feedback to the emitter(-ve input) of the driver transistor. I actually designed a 500MHz small signal amp with the exact same configuration, but of cause with gain!!! But I don't have to design to this kind of low distortion, I just hate to guess myself.
In fact I spent a day simulate the CFP, adjusting the loop gain of the two transistors by adjusting the emitter and collector resistor of the driver transistor and the emitter resistor of the power transistor. It seemed like there is a sweet spot of the loop gain where I got the least amount of HF harmonics. That's the reason I want to see whether there is any theory on how to lower the distortion on the CFP stage, how to adjust the current ratio, how to set the value of the resistors.
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