pjacobi said:
Yes, I know one can fine-tune the parameters to improve things,
but I don't understand FFT well enough to figure out how and
haven't bothered. Of course, if one can get such big savings in
run time, it is definitely worth it.
However, I tried your suggested settings above and get nowhere
close to the the performance you indicate, except in run time.
I get approx. -60dB 3rd order distorsion on the source signal!!!
The other odd harmonics also stick out and the general noise
floor is around -80dB.
BTW, be careful with notation like 9k765625 above. It seems that
LTSpice take it, but it is not Spice standard AFAIK. Normally I think
everything after the k is discarded, but maybe that is only for
letters? I might be wrong, though, and it is only letters that are
discarded, not digits.
Per-Anders,
I don't have the equipemnt to measure distorsion on these levels,
so building a prototype for the purpose of measuring is a bit
pointless for me, I think. Bulding for listening is another thing, though.
Don't bother too much about the very low distorsion figures. We
don't know how much they say about the distorsion in a real
circuit. However, I do think that comparative simulations like these
may say something about the relative behaviour of the circuits.
If circuit A gives a clearly lower distorsion than circuit B in a simulation,
I think it has a good chance of doing that in reality too. A lot of
other factors will enter, not the least noise as you mentioned.
However, I think the main reason for distorsion is still the intrinsic
exponential characteristic of BJTs, so I think/hope/assume/... that
simulations with idealized BJT models can tell something about the
relative merits of topologies. Note however, that my simulations
are only about distorsion so far. There are other important factors
such as phase and frequency response to consider for real
circuits, as you very well know. That is not unrelated, but brings
in more parameters so it should be kept as a separate issue,
I think.
As for conlcusions, I think that is too early. More simulations would
be useful and I am also trying to do some theoretical thinking
about it, with pen and paper, or lying on my back on the sofa.
I would also guess there are already ccomparative studies
between CFPs and followers in the literature that may already
have (some of) the answers. However, to quote Nobel prize
winner Anthony Leggett, "that is no reason not to do it yourself
because you always learn something from doing it".
I don't have the equipemnt to measure distorsion on these levels,
so building a prototype for the purpose of measuring is a bit
pointless for me, I think. Bulding for listening is another thing, though.
Don't bother too much about the very low distorsion figures. We
don't know how much they say about the distorsion in a real
circuit. However, I do think that comparative simulations like these
may say something about the relative behaviour of the circuits.
If circuit A gives a clearly lower distorsion than circuit B in a simulation,
I think it has a good chance of doing that in reality too. A lot of
other factors will enter, not the least noise as you mentioned.
However, I think the main reason for distorsion is still the intrinsic
exponential characteristic of BJTs, so I think/hope/assume/... that
simulations with idealized BJT models can tell something about the
relative merits of topologies. Note however, that my simulations
are only about distorsion so far. There are other important factors
such as phase and frequency response to consider for real
circuits, as you very well know. That is not unrelated, but brings
in more parameters so it should be kept as a separate issue,
I think.
As for conlcusions, I think that is too early. More simulations would
be useful and I am also trying to do some theoretical thinking
about it, with pen and paper, or lying on my back on the sofa.
I would also guess there are already ccomparative studies
between CFPs and followers in the literature that may already
have (some of) the answers. However, to quote Nobel prize
winner Anthony Leggett, "that is no reason not to do it yourself
because you always learn something from doing it".
Hi Per-Anders,
Yup, noise and everything will ruin the best theoretical numbers, but it doesn't hurt to get THD below 0.0003% (110dB) for a starting point.
The problem with actually building these suckers are
a) all semiconductors quickly run away and hide when I switch on the soldering iron (and right they are)
b) I'm lacking 90% of the necessary measuring equipment to let the prototypes tell me anything (but I may join forces with a more practically oriented friend of mine, real soon now)
Regards,
Peter Jacobi
peranders said:Christer, Peter, have you come to any conclusion? Maybe you should start making a prototypeOne good thing has come out of this and this is making narrow peaks in the fft chart. This I must test.
Note also guys that you have noise in real life.... -160 dB...!
Yup, noise and everything will ruin the best theoretical numbers, but it doesn't hurt to get THD below 0.0003% (110dB) for a starting point.
The problem with actually building these suckers are
a) all semiconductors quickly run away and hide when I switch on the soldering iron (and right they are)
b) I'm lacking 90% of the necessary measuring equipment to let the prototypes tell me anything (but I may join forces with a more practically oriented friend of mine, real soon now)
Regards,
Peter Jacobi
.... you could also settle with using your earspjacobi said:
You could use a sound card and Rightmark FFT, then you can get a picture of the performance better or worse than the soundcard.
http://audio.rightmark.org
SPICE trivia
Hi Christer,
Thanks for the warning about the non-standard notation, I assume you've changed it before your test run.
What flavour of SPICE are you running? Do you have the standard .fourier in addition to the graphical output you've shown? Any difference between these two?
As the set of parameter worked on .fourier, which is handled by the SPICE core itself, I did assume it will work for every SPICE which allows .fourier.
Perhaps some parameter tweaking (switchoff data compression, keep more digits etc) is necessary.
I didn't see THD on the input at all:
http://www.linearaudio.de/scratch/CFP.txt
Hi Christer,
Thanks for the warning about the non-standard notation, I assume you've changed it before your test run.
Christer said:
What flavour of SPICE are you running? Do you have the standard .fourier in addition to the graphical output you've shown? Any difference between these two?
As the set of parameter worked on .fourier, which is handled by the SPICE core itself, I did assume it will work for every SPICE which allows .fourier.
Perhaps some parameter tweaking (switchoff data compression, keep more digits etc) is necessary.
I didn't see THD on the input at all:
http://www.linearaudio.de/scratch/CFP.txt
Nice work Christer and pjacobi! A very interesting thread.
LTSpice seems to automatically choose the wrong stop time in the FFT dialog most, but not all of the time. I've seen very big improvements in the FFT residual from making the seemingly small change mentioned above by ojg. One strange quirk - if you choose Gear integration instead of trapezoid (just as a test, not generally recommended), LTSpice seems to get the stop time right every time. Weird. Another weird thing LTSpice does is automatically enable compression, which needs to be off to minimize the FFT residual. So I find that I'll get everything working right with a low residual, then quit LTSpice and start it again later. Then I always forget to go back into the control panel and disable compression again. I'll get a poor residual until I disable it.
Christer, I think the change in residual you're seeing with different topologies may be due to the time step issue. Based on info from the LTSpice mailing list, a good approach seems to be taking the number of cycles you're doing the FFT over, multiplying by the period, dividing by the number of FFT points and specifying this value as the minimum time step. If this number ends up being smaller than what SPICE would compute automatically for the time step, then the actual time steps used will be the same as what's needed for the FFT. If it's not, LTSpice needs to interpolate to get the FFT time points. This can be one reason for the poor residual.
ojg said:
LTSpice seems to automatically choose the wrong stop time in the FFT dialog most, but not all of the time. I've seen very big improvements in the FFT residual from making the seemingly small change mentioned above by ojg. One strange quirk - if you choose Gear integration instead of trapezoid (just as a test, not generally recommended), LTSpice seems to get the stop time right every time. Weird. Another weird thing LTSpice does is automatically enable compression, which needs to be off to minimize the FFT residual. So I find that I'll get everything working right with a low residual, then quit LTSpice and start it again later. Then I always forget to go back into the control panel and disable compression again. I'll get a poor residual until I disable it.
Christer, I think the change in residual you're seeing with different topologies may be due to the time step issue. Based on info from the LTSpice mailing list, a good approach seems to be taking the number of cycles you're doing the FFT over, multiplying by the period, dividing by the number of FFT points and specifying this value as the minimum time step. If this number ends up being smaller than what SPICE would compute automatically for the time step, then the actual time steps used will be the same as what's needed for the FFT. If it's not, LTSpice needs to interpolate to get the FFT time points. This can be one reason for the poor residual.
andy_c said:
Well, updating to the latest version of LTSpice (2.08m) seems to have fixed the problem with the incorrect stop time in the FFT dialog. I also tried the .FOURIER directive, and it worked great on Christer's circuit. Nice to have it calculate THD without having to do this manually! So I tried the .FOURIER command with my power amp simulation, and the results were 30-40 dB worse than my spectrum plots. I tried changing the time steps but wasn't able to improve this. It looks like care is required with .FOURIER to make sure it agrees with the spectral plots.
With the transient simulation set up as follows:
SINE(0 5 10k 0 0 0 12)
(12 cycles)
.tran 0 1.2e-3 0 3.051757813e-8
FFT start time = 7e-4
FFT stop time = 1.2e-3
Number of FFT points = 16384
(The time step is 5 cycles/16384)
I get a residual that's about 180 dB below the fundamental with a simulation time of about 3 seconds in Christer's circuit, using a 900 MHz Athlon. For the circuit without the CFP, I get
3rd harmonic = -79 dBc
5th harmonic = -105 dBc
7th harmonic = -131 dBc
same as Christer got.
Andy_c,
how did you get .fourier to work in LTSpice? It is not available in
the GUI, and explicitly adding it as a command in the schematic
didn't do anything. It is not long ago since I upgraded my version,
but maybe they have just included it??
BTW, I tried to rerun with a larger time step and switch off
compression. That made quite an improvement. It didn't give quite
the same figures, but close. It must obvioulsy be a lossy compression.
I'll make some more experiments with the other suggestions. My
PC shouldn't be that much slower than yours, so it seems worthwhile
experiimenting with.
how did you get .fourier to work in LTSpice? It is not available in
the GUI, and explicitly adding it as a command in the schematic
didn't do anything. It is not long ago since I upgraded my version,
but maybe they have just included it??
BTW, I tried to rerun with a larger time step and switch off
compression. That made quite an improvement. It didn't give quite
the same figures, but close. It must obvioulsy be a lossy compression.
I'll make some more experiments with the other suggestions. My
PC shouldn't be that much slower than yours, so it seems worthwhile
experiimenting with.
Sounds almost a bit Microsoftish that one should have to view the
errorlog to get ordinary runtime output.
Edit:
Yes, I just tried and it worked fine.
BTW, I just tried to run with a rather large time step, but without
compression and suddenly it made a lot of difference to use
windowing in the FFT. I got almost the same result as before using
a 1us time step and a Hann window. Previously windowing has
made little of no difference, That compression must be terribly lossy.
That makes an old question much more relevant, how to know
which window to use? Empirical tries only, or is there some
rule of thumb on this?
errorlog to get ordinary runtime output.
Edit:
Yes, I just tried and it worked fine.
BTW, I just tried to run with a rather large time step, but without
compression and suddenly it made a lot of difference to use
windowing in the FFT. I got almost the same result as before using
a 1us time step and a Hann window. Previously windowing has
made little of no difference, That compression must be terribly lossy.
That makes an old question much more relevant, how to know
which window to use? Empirical tries only, or is there some
rule of thumb on this?
andy_c said:Kind of like exiting via the "start" button?
Kind of what I was thinking of.
I just made a quick try as pjacobi explained and it worked to get
the fourier results that way. Too late do any more simulations
right now, but thanks for the help. I would never have have got
the idea of looking in the error log, especially since LTSPice gives
me the impression of being written by someone used to real OS's.
Christer & Guys,
This is very interesting. Can you pretty much specify the input impedance by simply setting the bias resistor? Could you achieve a 200K Zin, for example?
Christer, you say Class A. I presume by this you mean that none of the devices ever switches off; certainly the idle current is much lower than the 45mA you say it will swing into a load with 5Vpp.
Do you see application for the output stage of a power amplifier? For myself, having tried CFPs some time ago, I found that instability precluded this, but of course high idle Class A should be fine.
Cheers,
Hugh
This is very interesting. Can you pretty much specify the input impedance by simply setting the bias resistor? Could you achieve a 200K Zin, for example?
Christer, you say Class A. I presume by this you mean that none of the devices ever switches off; certainly the idle current is much lower than the 45mA you say it will swing into a load with 5Vpp.
Do you see application for the output stage of a power amplifier? For myself, having tried CFPs some time ago, I found that instability precluded this, but of course high idle Class A should be fine.
Cheers,
Hugh
Hi Aksa, All,
In the variants having current source biasing, Zin is simply "very high", with Rs you get 0.5 * beta * Rbias
The circuit in post #3 has Iq 30mA in the 'boosters'. As this is push-pull, up to 60mA output current is available, 45mA will have 7.5mA in one device and 52.5mA in the other.
Sure (for me at last). The idea is to build I giant current feedback OpAmp, input diamond, current mirrors, output diamond with CFP boosters.
But the instability wouldn't go away because of the nice looking topology alone. I've got a simulated amplifier stable with a outbuf buffer like that one:
http://www.linearaudio.de/scratch/DARL-BUFFER.pdf
http://www.linearaudio.de/scratch/DARL-BUFFER.asc
Note that the boosters became darlingtons, to have fast, high-beta BJTs in the diamond itself, so the whole would qualify for 'output triples'. Also complications arose to have some gain in the buffer, for the goal of getting the highest possible voltage swing.
Regards,
Peter Jacobi
AKSA said:
In the variants having current source biasing, Zin is simply "very high", with Rs you get 0.5 * beta * Rbias
AKSA said:
The circuit in post #3 has Iq 30mA in the 'boosters'. As this is push-pull, up to 60mA output current is available, 45mA will have 7.5mA in one device and 52.5mA in the other.
AKSA said:
Sure (for me at last). The idea is to build I giant current feedback OpAmp, input diamond, current mirrors, output diamond with CFP boosters.
But the instability wouldn't go away because of the nice looking topology alone. I've got a simulated amplifier stable with a outbuf buffer like that one:
http://www.linearaudio.de/scratch/DARL-BUFFER.pdf
http://www.linearaudio.de/scratch/DARL-BUFFER.asc
Note that the boosters became darlingtons, to have fast, high-beta BJTs in the diamond itself, so the whole would qualify for 'output triples'. Also complications arose to have some gain in the buffer, for the goal of getting the highest possible voltage swing.
Regards,
Peter Jacobi
pjacobi said:
Maybe I am too tired to think right now, but wont the CCS be
in parallel with beta*Re for the output stage (assuming the
follower version). This shuld be the limiting factor, so very high
input Z seems somewhat diffiult to achieve for low Re values.
I might be wrong though, considering the late hour.
Agree, although, right now, I don't remember the exact figures
I got. I think I posted them earlier, though.
For the third question I am not so sure it would work without
some temp. comp. for the output bias, but maybe the buffer
actually does this withouth explicit temp. comp. I will have to think more about that.
Christer said:
You are right for then pure diamond.
For the #3 circuit, most of the output conductance is hidden from the diamond by the booster BJTs, which take almost all of the current swing. So the diamond's output stage is effectively also driving current sources. (Of value Vbe(Q6)/R10 = about 7mA).
Count this on the 'pro' side for using boosters. Without them, we would indeed be at beta1*beta2*Rload.
Regards,
Peter Jacobi
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