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Old 26th November 2014, 07:54 PM   #1
mcd99uk is offline mcd99uk  United Kingdom
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Default Amp designed during lunch breaks

Hi All,

Decided that as I waste most of my time during lunch breaks at work decided it might be a good idea to install LTSpice and design amps instead. Well here is the result so far.

It is a simplified SuperTis (by Edmond Stewart) front end with some OIC MI compensation (I think) and non error corrected OPS.

The output inductor values and vbe multiplier component values are guessed at present. Also, decoupling has been ommitted for clarity of schematic.

Here is the schematic along with the latest .asc

Edit: Latest .asc now here Amp designed during lunch breaks

Paul

Edit: Loop analysis tools provided by David Zan.
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File Type: jpg Draft5.jpg (302.1 KB, 489 views)
Attached Files
File Type: asc Draft5.asc (14.4 KB, 18 views)

Last edited by mcd99uk; 8th December 2014 at 08:54 PM.
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Old 27th November 2014, 08:55 AM   #2
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Default long lunch breaks?


looks very promising!
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Old 27th November 2014, 09:19 AM   #3
mcd99uk is offline mcd99uk  United Kingdom
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Quote:
Originally Posted by padamiecki View Post
Long lunch breaks
You know they are.

Quote:
Originally Posted by padamiecki View Post

looks very promising!
Thank you.

Hopefully... It will be a lot more promising once a strip board prototype has been built.

There is still some development to go. Been concentrating on loop stability up till now. Today's lunch break will be the start of working out better SOA protection for the output stage. Probably go for a dual slope.

Paul
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Old 27th November 2014, 09:24 AM   #4
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Quote:
Originally Posted by mcd99uk View Post
Hopefully... It will be a lot more promising once a strip board prototype has been built.

There is still some development to go...
in my sims I found strong oscillations @~10MHz but maybe because it was only more or less rough schematic/idea or different models (I use cordell-models.txt)
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Old 27th November 2014, 09:29 AM   #5
mcd99uk is offline mcd99uk  United Kingdom
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Quote:
Originally Posted by padamiecki View Post
in my sims I found strong oscillations @~10MHz but maybe because it was only more or less rough schematic/idea or different models (I use cordell-models.txt)
Interesting...

I too use Cordell models and where necessary in built LTSpice models.

How did you manage to get this amp to oscillate? I'm still only really a beginner (/ improver ) with amplifier design.

Thank you for taking the time to have a look at my amp.
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Old 27th November 2014, 10:03 AM   #6
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this is mine graph of ac small signal, however sine during transient sims is OK
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Old 27th November 2014, 10:15 AM   #7
mcd99uk is offline mcd99uk  United Kingdom
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Pawel,

Try deleting the loop analysis tools. There is some sort of interaction going on between the tian probes and the small signal AC analysis.

Here is my plot with tian probes removed. Still shows a problem but at least it looks a little better.

Paul
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Old 3rd December 2014, 09:15 AM   #8
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Originally Posted by mcd99uk View Post
...delet[e] the loop analysis tools. There is some sort of interaction
Hey, the tools are fine.
Your Ltspice has an error, there is no .SET statement.
The correct syntax is
.Param Tn=0 Tm=0

Best wishes
David
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Old 3rd December 2014, 09:31 AM   #9
mcd99uk is offline mcd99uk  United Kingdom
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Quote:
Originally Posted by Dave Zan View Post
Hey, the tools are fine.
The tools are the best. It's the user in this case...

Have I got the placement correct?


Quote:
Originally Posted by Dave Zan View Post
Your Ltspice has an error, there is no .SET statement.
The correct syntax is
.Param Tn=0 Tm=0

Best wishes
David
And the most embarrassing bit for me is that we discussed this not so long ago with Damir.
Will add the correction. Thank you for pointing this out (again).

There will be an update on this project soon. Got new values for the Thiele / Cherry output network.

Paul

Last edited by mcd99uk; 3rd December 2014 at 09:39 AM.
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Old 3rd December 2014, 09:59 AM   #10
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Originally Posted by mcd99uk View Post
...the placement correct?
Not quite for the Zan/Z0 nodes, I suspect. Just back from a few days in Syn city (Sydney) so a bit tired, always lots of posts while I am otherwise occupied
But I think you need to check the outer loop with a probe from the junction of R13 - R14 to the bases of the input transistors Q3 and Q4.
Your probe position for Edmond's cascode VAS looks correct but I have never checked that particular circuit so will think a bit more to be sure.

Best wishes
David
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