CPLD vs. uC for PGA2310 - diyAudio
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Old 20th January 2004, 03:18 AM   #1
ajm8372 is offline ajm8372  United States
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Default CPLD vs. uC for PGA2310

I have seen several threads here about the PGA2310 and it seems like most people are using a microcontroller to control it. What are some advantages the micro has over a CPLD? I am asking because I am much more familiar with CPLDs and have access to software. I know the CPLD would require an external clock. I am guessing a 100kHz clock would do fine for the PGA and whatever other controls I include. Would this clock cause any interference with the rest of my analog circuitry?
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Old 20th January 2004, 06:09 AM   #2
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Default cpld vs uc

What is more easy for you !
I am quite familiar with C and VHDl/Verilog and i do not see a real difficulty in both.
Since i also connected an LCD i used a micro-controller, easier to store text and such !

grtz

Simon
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Old 20th January 2004, 01:20 PM   #3
ajm8372 is offline ajm8372  United States
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Yea I was thinking I may have to include either an NVRAM or flash to store some of the charachters and volume configurations. I would like for the preamp to retrieve the previous volume configuration when it starts up.
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Old 20th January 2004, 06:49 PM   #4
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Default go for the uc

i think this will give you a bit more flexibility !
And if you need a kick start........... i can help !

grtz

Simon
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Old 20th January 2004, 07:18 PM   #5
azira is offline azira  United States
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I say CPLD... if you're going basic functions, uCPU if you want to start doing more fancy stuff.

But 10 lines of VHDL in your CPLD (for debouncing switches and sending the signal to your PGA) will be 100 lines of code in a uCPU.

Either way you'll want an analog gnd and a digital gnd. Your digital gnd should be a seperate point that is connected to your analog gnd with one wire... decouple your digital logic to your digital gnd too.
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Old 20th January 2004, 07:26 PM   #6
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I use a Xilinx XC9572XL CPLD to control three PGA2310s. There's an up/down switch to increment or decrement the data that's put on the SPI bus and I also put in a two second power-up delay to drive the anti-thump relays.

There's a couple of pics and a scope trace of the SPI in this thread:
Problem controlling a PGA2310

Let me know if you'd like the source code (VHDL).

Nice one,
David.
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Old 20th January 2004, 11:40 PM   #7
ajm8372 is offline ajm8372  United States
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Default going with CPLD...

It looks like I will go with a CPLD then. It helps that I use VHDL very often at my job and have access to all of the Altera programming software/hardware. If I ever get into anything more advanced (adding IR remote or something..) i will take a harder look at the micro.

Thanks for all the help!
jeremy
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