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Ultra-high performance, yet rather simple - hybrid and more!
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Old 27th September 2014, 06:53 AM   #21
vzaichenko is offline vzaichenko  Russian Federation
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Ultra-high performance, yet rather simple - hybrid and more!
Quote:
Originally Posted by didiet78 View Post
can i use k177-gr or k170-bl ? Any change needed ?
Hi Didiet,

You can use k170 (both gr and bl). Optimal source degeneration resistors (R32, R54) value for jFETs will be 220R (actually, same for k117). Drain current is stabilized at 1.54mA per shoulder here.

k170 is a little bit slower than k117, but also a bit lower-noise one, however in this particular case you will most likely not notice the difference (because of the high GNFB loop gain in this design). In terms of SOA - also no problem.

Cheers,
Valery
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Old 28th September 2014, 02:49 AM   #22
didiet78 is offline didiet78  Indonesia
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So i will fine with > 2ma Idds ?
Any updated schematic ?
I'm trying to make pcb for FetSuMo, and find you layout have servo. Which component i need to change for 35-45V supply ?

Thanks.
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Old 28th September 2014, 02:53 AM   #23
Bigun is offline Bigun  Canada
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Ultra-high performance, yet rather simple - hybrid and more!
Quote:
Originally Posted by vzaichenko View Post
Developed the layout for IPS section. 3"x5.7" double layer.
That's a nice looking pcb layout. I am thinking the same as you for my own hybrid - provide footprints for SS IPS just in case. But I do like to see a tube in there
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Old 28th September 2014, 08:12 AM   #24
vzaichenko is offline vzaichenko  Russian Federation
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Quote:
Originally Posted by Bigun View Post
But I do like to see a tube in there


I did some comparisons.
Although the tube gives the lowest gain, comparing to jfet and bjt at the input, it provides the best linearity, maintaining very low noise (as I can see in my earlier prototypes), and glowing in the dark.
Excellent, hard to beat combination!
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Old 28th September 2014, 08:37 AM   #25
vzaichenko is offline vzaichenko  Russian Federation
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Arrow PCB update

Just finished the OPS board.
Same size - 3"x5.7" - as IPS one.
Coincidence
Will order the first "pilot" pair tomorrow...
Attached Images
File Type: jpg #01-TubSuMo-IPS-PCB.JPG (310.5 KB, 1460 views)
File Type: jpg #01-TubSuMo-OPS-PCB.JPG (243.3 KB, 1385 views)
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Old 28th September 2014, 10:22 AM   #26
vzaichenko is offline vzaichenko  Russian Federation
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Arrow +/-40V supply k170 option

Quote:
Originally Posted by didiet78 View Post
So i will fine with > 2ma Idds ?
Any updated schematic ?
I'm trying to make pcb for FetSuMo, and find you layout have servo. Which component i need to change for 35-45V supply ?

Thanks.
Hi Didiet,

Idss shows the value of drain current at zero g-s offset. In our case, the drain current is set by CCS at 1.54 mA per jfet, which is fine for both k170 and k117 at any rating (gr and bl), g-s offset will setup automatically (the circuit is self-balancing).

Despite the fact I use DC servo, I have left the trim-pot between jfet sources - it will be possible to micro-trim for the lowest distortion (although it will be low enough even with no trimming).

Here is the schematic, adjusted for +/-40V supply, this one will work fine in +/-35V to +/-45V range of supply voltages, giving more or less 50W at 8 ohm output power. In fact, in this case you can use just one pair of output FETs - more than enough for this power level (even for 100W at 4 ohm).

Use the small local heatsinks for U3, U4 (around 0.35W dissipation here).

Cheers,
Valery

P.S. You can also add some more electrolytics to the power rails - I omit them for sim purposes (they slow-down the model as it runs at 1/10-th of the real time).
Attached Images
File Type: jpg !02-FetSuMo-sk170-40V-sch.JPG (389.9 KB, 1417 views)
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Last edited by vzaichenko; 28th September 2014 at 10:29 AM.
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Old 28th September 2014, 12:53 PM   #27
borys is offline borys  Ireland
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vzaichenko
What a nice VAS stage !! I must be blind that didnt spoted it before.
Looks really promising. Looking fore further updates.
thx
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Old 28th September 2014, 01:18 PM   #28
didiet78 is offline didiet78  Indonesia
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Thanks
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Old 28th September 2014, 04:59 PM   #29
dadod is offline dadod  Croatia
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Quote:
Originally Posted by vzaichenko View Post
Hi Didiet,

Idss shows the value of drain current at zero g-s offset. In our case, the drain current is set by CCS at 1.54 mA per jfet, which is fine for both k170 and k117 at any rating (gr and bl), g-s offset will setup automatically (the circuit is self-balancing).

Despite the fact I use DC servo, I have left the trim-pot between jfet sources - it will be possible to micro-trim for the lowest distortion (although it will be low enough even with no trimming).

Here is the schematic, adjusted for +/-40V supply, this one will work fine in +/-35V to +/-45V range of supply voltages, giving more or less 50W at 8 ohm output power. In fact, in this case you can use just one pair of output FETs - more than enough for this power level (even for 100W at 4 ohm).

Use the small local heatsinks for U3, U4 (around 0.35W dissipation here).

Cheers,
Valery

P.S. You can also add some more electrolytics to the power rails - I omit them for sim purposes (they slow-down the model as it runs at 1/10-th of the real time).
Valery, I have a few question about this amp.

1. Why you use so low current for 2SK170, jfet works best with drain current close to its Idss?
2. Why so high jfet degeneration, it is waste of gain?
3. Why use of blue LED to bias cascade, the bleu LED has highest noise?
4. Why you use shun resistors (R23, R24) in the VAS to lower the gain? Is it not better to use it (the gain) in NFB, locally perhaps?
5. I suggest you to use bjt bias spreader instead simple resistor, lower impedance, and you don't put it on the heathsink of course.
6. I think that you use to low degeneration in bjt LTPs.

Just mine opinion, Damir

PS. You use low resolution spice, it's time to switch to LTspice, and then you can share the .asc files as most people here use LTspice.

Last edited by dadod; 28th September 2014 at 05:02 PM.
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Old 28th September 2014, 06:01 PM   #30
vzaichenko is offline vzaichenko  Russian Federation
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Ultra-high performance, yet rather simple - hybrid and more!
Hi Damir! My answers are inline below:

1. Why you use so low current for 2SK170, jfet works best with drain current close to its Idss?
*** In many cases, higher drain current = higher noise. 3mA tail current is a sort of a practical optimum (based on experience). Also, my initial thinking was 2SK117, for 2SK170 quiescent current may be set slightly higher (4-4.5mA at the tail?).

2. Why so high jfet degeneration, it is waste of gain?
*** OLG of this design is very high - with low degeneration you will have 120db easily, maybe even more. In such situation, it's better to use some of it for local NFB (which degeneration is), ensuring better linearity and frequency response of particular cascade (LTP in this case).
With regards to GNFB loop gain, "the more is the better" is not the right approach. If you want smooth transients handling, you need to keep each stage's OLG under control.
Experiments with my earlier hybrid showed the best results with the following gain distribution:
1-st LTP 10.8 db
2-nd LTP 18.7 db
VAS 45.7 db
Overall OLG 75.3 db
CLG 28.5 db
LG 46.8 db

So, I don't want to have the first LTP OLG higher than, say, 12db.

3. Why use of blue LED to bias cascade, the bleu LED has highest noise?
*** This is a good point - I will a slot for the 2-nd LED on each side, so that I will test the live prototype with the blue ones and with a pair of red ones. Slightly higher offset, but never mind - it will be very interesting to see what practical difference noise-wise will be observed.

4. Why you use shun resistors (R23, R24) in the VAS to lower the gain? Is it not better to use it (the gain) in NFB, locally perhaps?
*** Also a good question. I tested this kind of shunt load for VAS with different OPS topologies some time ago. When you have a "complex", non-linear, input impedance of your OPS - this is what you have in many cases and this is what we have here, loading VAS with a constant resistive load helps to "mitigate" this non-linearity. In this particular case, the shunt us rather high R, I saw designs (well performing!), where VAS was loaded with 7.5K. Exactly for the purpose I just mentioned.
Again, we've got a bunch of excessive gain to spend here

5. I suggest you to use bjt bias spreader instead simple resistor, lower impedance, and you don't put it on the heathsink of course.
*** Possible option, again - worth practical testing. Resistor is low here, so - should not be a problem. But I will try a simple spreader as an experiment.

6. I think that you use to low degeneration in bjt LTPs.
*** This pair of LTPs doesn't need to be too much balanced individually (unlike the first LTP), so... again a question - how much gain I'd like to drop here. rather difficult to understand from the simulation, so I will make some tests on the prototype. But the point is good - maybe a bit higher degeneration will allow balancing them between each-other. Need to see the real spectrum to understand if this is really the case.

Thank you for the questions - made me think once again about some things... which is always good

Cheers,
Valery
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