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Hi Jason. I would like 2+ Symasui please. Do all transistors need to be match?( also those 0.22R resistors).
Quan

Hi Quan,

I think you may have misread the silk screen, there are no 0R22 resistors on the Symasui IPS, but I could see the confusion with R22 being a 22R value. When I put the value on the silk screen it will always be 'inside' the silk pattern for the device, the schematic designator will always be visible when the device is installed.

I would do a basic matching of the TO-92 devices, no need for obsessive pursuits.
 
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Resistors can be used to verify the VAS current but the IPS is best tested without them. Just tie the NFB, PD and ND together and measure the output off the NFB point. You will notice with the CFA designs the VAS is heavily loaded by the low impedance FB network and this is less of an issue with the VFA designs. Still, it is nice to be able to run the IPS designs independently.
 
Resistors can be used to verify the VAS current but the IPS is best tested without them. Just tie the NFB, PD and ND together and measure the output off the NFB point. You will notice with the CFA designs the VAS is heavily loaded by the low impedance FB network and this is less of an issue with the VFA designs. Still, it is nice to be able to run the IPS designs independently.
Thanks Jason, can you show it on simple diagram ?.
Quan
 
Hi Jason, may be these questions should be over the other thread but does q7 and Q10 on CFA IPS needs to be thermocouple?. How much heat sink do they need?. I can see the space for a flat pierce of aluminum only. I have a couple of small finned heat sink size 2cmX1cmX0.4mm. Would they be ok for those mje 340/350?. TIA.
Quan
 
Hi Jason, may be these questions should be over the other thread but does q7 and Q10 on CFA IPS needs to be thermocouple?. How much heat sink do they need?. I can see the space for a flat pierce of aluminum only. I have a couple of small finned heat sink size 2cmX1cmX0.4mm. Would they be ok for those mje 340/350?. TIA.
Quan

Very minimal heat sinking is required, so a small piece of aluminum sheet is fine. I tested mine without any heat sink at all at +/-45V without any issue.
 
Make sure you are printing at 100% and not allowing any scaling. There are two distinct templates, one for the first run which I was pretty sure you got and one for the final, current, version. The holes for the PCB corners and the main output VBE positions are different so it is important to be sure which ones you have. I have printed the templates and can verify they line up. If need be I can send them to you in a different format. PM me with an email address and I'll send you both versions in PDF and an image format (bitmap maybe - I have to see what export options the CAD program has).
 
Hi Jason, i just don't want to clog up the thread but running into some trouble with the OPS. I used 15kR across V/PD, ND/-V. I could not get any measurement at RE(0.22R). R113 (68R) measured 5.67V!!!, R110 measured 11.2V. The pre-driver HS toasting hot with alum plate.I used all parts as per your schematic. BTW IPS(CFX-3H) is good and ready to go.
Quan
 
Well, 15k should do for most testing purposes with respect to running the OPS on its own. You say you have tons of bias in the pre-driver / driver but none in the outputs? What are you running for rail voltages?

You have connected the two G2 points with a wire under the board?
 
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Well, 15k should do for most testing purposes with respect to running the OPS on its own. You say you have tons of bias in the pre-driver / driver but none in the outputs? What are you running for rail voltages?

You have connected the two G2 points with a wire under the board?
Thanks Jason. Yes i did connect the ground together and connected 114/115. The rails are +/- 67VDC. I measured across 0.22R but got nothing despite adjusting the bias. The R113 (68R) measured >5V, R110 measure 11.2V.
Quan
 
I could not adjust the bias at all. Just a couple of pictures. I suspect may be one of the trannie are position incorrectly.
 

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