Preliminary design for a 50WPC amp. This being a full power version of a preliminary, "proof of concept" design that sounded very good indeed, and which are still serving as computer speeks. Time to scale up.
For this, the finals are the 2SC3281/2SA1302 NPN/PNP complimentaries, the "6V6" of power BJTs. These have some excellent linearity, less susceptible to gm fall-off under load, and will work here at this power level while staying in spec (will need a heatsink to hold the temp to 85deg C). The finals connected as Sziklai Pairs, since this topology sounds best, in my experience, better than EF -> EF. It's not used as often as it should be.
The front end is rather conventional, and needs cascoding due to the voltage limit of the low noise, high HFE NPNs (2N5088 -- I have a bunch). HHE= 300 (min) to keep the base currents down, and with it, DC offset. I have enough of these to select a really good matched pairs. These are also specced as being low noise, though the proof of concept design with "transistors anonymous" from Rat Shack is nice and quiet with no signal.
The inputs to the VAS are buffered with emitter followers (a design departure from the proof of concept) as is the use of a current mirror as the active collector load. The original didn't use a current mirror.
For this, the finals are the 2SC3281/2SA1302 NPN/PNP complimentaries, the "6V6" of power BJTs. These have some excellent linearity, less susceptible to gm fall-off under load, and will work here at this power level while staying in spec (will need a heatsink to hold the temp to 85deg C). The finals connected as Sziklai Pairs, since this topology sounds best, in my experience, better than EF -> EF. It's not used as often as it should be.
The front end is rather conventional, and needs cascoding due to the voltage limit of the low noise, high HFE NPNs (2N5088 -- I have a bunch). HHE= 300 (min) to keep the base currents down, and with it, DC offset. I have enough of these to select a really good matched pairs. These are also specced as being low noise, though the proof of concept design with "transistors anonymous" from Rat Shack is nice and quiet with no signal.
The inputs to the VAS are buffered with emitter followers (a design departure from the proof of concept) as is the use of a current mirror as the active collector load. The original didn't use a current mirror.
Attachments
Last edited:
Hi Miles, looks good. I also like Sziklai pairs, however I like Bryston-type-of-topology even better.
One thing came to my mind right away - did you think about using CCS's instead of R11, R12 - to linearize the EF loads to the limit? May help to save some PPM... easy to check with sim.
BR,
Valery
One thing came to my mind right away - did you think about using CCS's instead of R11, R12 - to linearize the EF loads to the limit? May help to save some PPM... easy to check with sim.
BR,
Valery
Interesting design.
A side note, I see you have put base stoppers on the OP devices (i.e. R23).
I think , since the CFP is a compond transistor, that they are more effective on the base of the driver. I put them directly on the base of the OP as well only if the OP is wired outside the PCB (i.e. a TO3 device). And yes, CFP with wired OP can be done and it has its own advantages (thermal stability) vs EF.
A side note, I see you have put base stoppers on the OP devices (i.e. R23).
I think , since the CFP is a compond transistor, that they are more effective on the base of the driver. I put them directly on the base of the OP as well only if the OP is wired outside the PCB (i.e. a TO3 device). And yes, CFP with wired OP can be done and it has its own advantages (thermal stability) vs EF.
One thing came to my mind right away - did you think about using CCS's instead of R11, R12 - to linearize the EF loads to the limit? May help to save some PPM... easy to check with sim.
BR,
Valery
I don't think it would make very much difference. The signal levels are quite low at that point, making for less distortion anyway. I've used these sort of passive loaded followers with good results before, and they're quite "transparent".
Interesting design.
A side note, I see you have put base stoppers on the OP devices (i.e. R23).
I think , since the CFP is a compond transistor, that they are more effective on the base of the driver. I put them directly on the base of the OP as well only if the OP is wired outside the PCB (i.e. a TO3 device). And yes, CFP with wired OP can be done and it has its own advantages (thermal stability) vs EF.
This was the intent: to connect the finals off the board for constructional considerations. I didn't include these in the prototype, as that had the finals on-board (needed to fit into a Rat Shack project box to make it into computer speeks). As for what the design will be needing in practice, that remains to be seen once I get this project underway, and can finalize a complete design. That's all I got so far: a preliminary schemo to work from.
Last edited:
- Status
- Not open for further replies.