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Old 12th October 2013, 07:33 PM   #21
danny92 is offline danny92  Portugal
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Hi everyone,

Thank you very much for your help astx, I will download your models astx, and I will to take a look at the SOA discussions of your design.
I've already the Michael Kiwanuka's SOA papers, I'm thinking about a dual slope VI limiter like the one on figure 41, it's a good idea?
I will try to trace the curves on LTSpice.

PS: Q15/Q16 are the cascode transistors of the IPS (TCS), not EF pair, do you think my EF pair is unstable? I should add something to become stable?

Zobel network from gate to drain, or from base to collector, are a method to gain stability at higher frequencies (> 10-15 MHz), but degrades the phase margin very much, I had it included in my project, but I've removed them because of this problems
Now I use another method, base and gate stopper resistors to do a similar effect, they reduce the bandwidth of the transistor to the order of a few MHz (1-10 MHz), because they do a zobel network against Cpi/Cgs, they also introduce some phase lag, but it's acceptable.

Best regards,
Daniel
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Last edited by danny92; 12th October 2013 at 07:54 PM.
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Old 13th October 2013, 11:20 AM   #22
astx is offline astx  Austria
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Quote:
Originally Posted by danny92 View Post
I've already the Michael Kiwanuka's SOA papers, I'm thinking about a dual slope VI limiter like the one on figure 41, it's a good idea?
Lowest THD figures using a single or dual slope VI limiter is nearly impossible. You have to decide: lowest THD or highest amplifier safety.

Quote:
Originally Posted by danny92 View Post
PS: Q15/Q16 are the cascode transistors of the IPS (TCS), not EF pair, do you think my EF pair is unstable? I should add something to become stable?
IMHO these are also EFs and may oscillate.

BR, Toni
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Old 13th October 2013, 03:29 PM   #23
danny92 is offline danny92  Portugal
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Hi everyone, and thank you for your help astx

I think that Q15/Q16 are common base, not EF (emitter-followers), because the constant voltage source is at the base and the signal enters the emitter and exits by the collector, creating some voltage gain, but no current gain (Ai = beta/(beta+1)), correct me if I'm wrong, please.
In an emitter follower (common collector), the constant voltage source is at the collector and the signal enters the base and exits by the emitter, this topology is a current amplifier, without voltage gain (Av aprox. 0.9-0.99), Ai = beta+1.
In a common emitter the constant current source is at the emitter and the signal enters the base and exits by the collector, this amplifier has both voltage and current gain, Av aprox [(-gm*Rc)/Re)], and Ai = beta.

PS:
As about the EF I've made with MJE15032 and MJE15033 it is stable?
I really want a dual-slope VI limiter, I expect that THD figures can get worse, but that's not a big problem, the amplifier should survive to real world conditions, like shorts and overloads.
If you want to make an amplifier similar to this one or based on this one (with the low THD figures presented), you can skip the VI limiter, and use fuse protection, or current limiting at the power supply.

Best regards,
Daniel

Last edited by danny92; 13th October 2013 at 03:46 PM.
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Old 13th October 2013, 04:30 PM   #24
danny92 is offline danny92  Portugal
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Hi everyone,

I'm sorry in common base Av = gm*Rc, and in common emitter Av aprox (Rc/Re), if Rc*gm >> 1.
I really wanted to make the SOA curves for the output stage, to incorporate the figure 41 circuit of Michael Kiwanuka's papers, can anyone help me here?
I know that this can be made using LTSpice, but I don't know the commands, I've looked at the astx amplifier SOA discussions and there are very valuable information there, but I don't what LTspice commands I should use to draw the SOA curves.
Best regards,
Daniel
Attached Files
File Type: asc Amp7_tmc_hb5_s.asc (16.8 KB, 9 views)
File Type: txt Cordell Models.txt (19.2 KB, 7 views)
File Type: pdf soaprot_12-03-2012 (2).pdf (637.5 KB, 19 views)

Last edited by danny92; 13th October 2013 at 04:52 PM.
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Old 14th October 2013, 01:42 AM   #25
danny92 is offline danny92  Portugal
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Hi everyone,

I've replaced the simple current mirror at the VAS by an improved current mirror, THD1 characteristics remain the same, THD20 characteristics are 10 ppm better, do you think that this change is a good idea?
And about the resistors at base of the TCS/TIS cascode transistors are a good or bad idea?

Best regards,
Daniel
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Old 14th October 2013, 04:03 AM   #26
danny92 is offline danny92  Portugal
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Hi everyone,

I've made a few more changes:

- I replaced the VAS 2N5551 for a BC550
- I replaced the Vbe multiplier for a BC550

Now simulated THD20 figures at 100W/8R and 200W/4R are both of less than 0.004 % and THD1 figures are of less than 0.00003 % for the 8 ohm load and less than 0.00004 for the 4 ohm load

What's your opinion about this changes?

I'm a little concerned about the output stage because I'm not thinking in incorporate zobels (base to collector or gate to drain) due to the increased phase lag that they introduce. So do you think that the base/gate stopper resistors are sufficient, they cutoff for -3dB at less than 5 MHz at the predrivers and less than 1 MHz at the output MOSFETs. This can be safe?

Best regards,
Daniel
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File Type: jpg amp7_tmc_hb5_s_test.jpg (157.6 KB, 265 views)
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File Type: asc Amp7_tmc_hb5_s_test.asc (17.0 KB, 6 views)

Last edited by danny92; 14th October 2013 at 04:27 AM.
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Old 14th October 2013, 06:49 AM   #27
mcd99uk is offline mcd99uk  United Kingdom
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About drivers. Bootstrapped drivers may be the way forward to get rid of those MJE devices if you're having problems getting alternatives. That way you can use either BC3x7s or the 2N pair.
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Old 14th October 2013, 09:12 AM   #28
AndrewT is online now AndrewT  Scotland
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You are running somewhere around 40 to 50mA (2W to 3W of Pq) in your drivers.
This gets you up the fT curve.
Using 15034/5 that has an even higher fT and pushing Pq to around 5W will probably speed up your driver stage quite significantly.
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Old 14th October 2013, 10:32 AM   #29
danny92 is offline danny92  Portugal
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Hi everyone,
Thank you very much for your suggestions, I appreciate your help.
I could try the MJE15034/35, with 100-110 mA if I has the LTSpice models for those transistors. Can you give me the models, please?
I'm really sorry mcd99uk, but I don't know what is a bootstrapped driver. Can you explain it to me, please?

Best regards,
Daniel
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Old 14th October 2013, 06:17 PM   #30
mcd99uk is offline mcd99uk  United Kingdom
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Here is an example of bootstrapped driver. Set Driver Bias current to around 5mA.

Set voltages at nodes where the 10R resistors meet the 5k6 nodes to about the max Vgs you want to allow. Changing the 5K6 resistors as well as changing the bias sets this voltage.

Using this method means you don't need gate zeners.
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