BUZ901/906 poor modeling?

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Hi everyone,

I'm testing some amplifier topologies with BUZ901/906 pair of output MOSFETs, and I've noticed that both in TINA and LTSpice I've higher THD20 with this devices than with other devices, I'm using the gate stopper resistors as suggested in Semelab's application note about ALFETs. With BJT output, IRFPs 240/9240 and Toshiba transistors the distortion seems lower, I'm still using gate stopper resistors but with diferente values adapted to the respective Ciss. I want to know if someone knows if this is a model's problem or the BUZ901/906 pair are not suitable for audio?

I'm sorry for not showing any circuit, I have them in another PC I will post them latter.

Best regards,
Daniel Almeida
 
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You do realise these are Lateral Mosfets, not Hexfets like IRP240/9240? There are many differences in construction, biasing and thermal coefficients between the types and you certainly won't good results just dropping them in the same circuit without close attention to application notes, data sheets and recommendations at least.

Close families to these are the Exicon and Alfet range of Latfets also made by Semelab and also similar are Renesas 2SK1058/J162 and similar. Everything else is basically Hexfet, as far as popular audio mosfets are concerned. You may be aware that the models for these are likely poor too, so compare results to Renesas parts which prove to give similar results to other Latfets in real amplifiers.

Yep, simulation is only as good as the models available to you.
 
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Thank you very much,

I will try the Renesas pair. Every time I change the devices, I set the bias voltage, and the respective gate stopper resistors. But I know that IRFP are verticals intended for switching mode power supplies, and BUZ are more for linear applications, like power amplifiers. Laterals have lower Vgs(on) voltages compared with verticals. The positive termal coeficient of the channel is true?
Best regards,
Daniel Almeida
 
This is some useful wisdom from MagicBox.

If you want to have a fast MOSFET outputstage that deals with local oscillation you'll have to do this:

Use your desired low gate stopper in the 10 - 22 Ohms region (I use 15Ohms). To shut up the local oscillation, you have to mount a ceramic cap directly to the soldering joints of the Drain and Gate. Eventhough it looks like you are just loading the input with the power supply, it is in effect a local feedback at high frequencies. (Consider the drain the inverting output to the non-inverting gate input, it then starts to look like the capacitive feedback as you see with opamps, from output to inverting input).

In my MF80 project I silenced all parasitic oscillations in the FETs by putting a 47pF ceramic directly across the Drain and Gate pins while using a 15R gatestopper. Without the cap, I would have a 2V p-p 85MHz (!!) local oscillation.

So no, don't use gate snubbers. Use the concept of local capacitive feedback by viewing the FET as an inverting amplifier at the drain node.

I must note though, that in the simulator the feedback caps don't make any difference and that's mostly because the inductive parasitics are not modeled well or at all. I've been developing this point of view on the real thing: my MF80 amp.
 
Hello mcd99uk and thank you once more for your help,

Do you think I should use a capacitor from drain to gate?
What are the best values 10-100pF?
How the capacitor is calculated?
A 330 ohm resistor for N-channel, and 220 ohm resistor for P-channel as suggested in Semelab's app note don't stop the oscillations?

Best regards,
Daniel Almeida
 
I had a little battle with oscillations with my prototype. It turns out you can get a clue from the frequency of the oscillations.

If in the range of 0 to 10MHz then check for control loop problems. For example, closed loop response peaks and in my case too high a ULGF.

If the oscillations are in the tens of MHz a Drain to Gate cap could work. They are likely to be local. I determined the value by experimentation. Ended up with 22pF. One thing to watch out for is the possibility of loosing phase margin.
 
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Thank you for you fast repplies and for your great support,

I see, so this combination of the capacitor and the resistor gives a better high frequency response, right?
They improve THD20, right?
Could you show me a circuit using this compensation method?

Best regards,
Daniel Almeida
 
You number one priority in amp design is stability. There's no use having an amp that oscillates and is unstable.

The combination of gate stopper and Gate to Drain capacitors serve to stabilize /damp the oscillations. They will do nothing for THD20. They will adversely affect phase margin and probably gain margin though.

Here's a schematic. Inductors L2 to L5 represent PCB parasitics. Ignore component values just look at the topology and re-read Magicbox's explanation.
 

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I didn't use this capacitor at first and in future projects I'd still do the same. But its your project...

Bench power supply would be better than fuses. I was lucky to have a couple of bench supplies so have no experience in other methods of current limitation. Others will have more knowledge of these things.

What sort of power are you looking to run?

Paul
 
I wanted to deliver 2x200 Wrms into 4 ohm load, I was thinking about using a 625VA toroidal transformer, and a rectifier, for the IPS-VAS I'm thinking about using a regulator.
I don't have a bench supply.
You don't use the capacitor from drain to gate? You said you're using a 22 pF capacitor.

Best regards,
Daniel Almeida
 
I do use a G-D capacitor now but the initial design didn't include one. The G-D capacitor was added at the prototype stage.

In any future project I would start off without this cap and add it if it was necessary.


If using regulated front end supplies you will need to consider a way of boosting the IPS/VAS rails prior to regulation.

Regarding the transformer some people use the 2VA per 1W output rule.
 
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