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Old 12th September 2013, 01:33 PM   #1
danny92 is offline danny92  Portugal
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Default Open loop gain peaking

Hi everyone,

I'm testing several IPS-VAS topologies based on Bob Cordell's designs, and I've noticed that the JFET input amps seem to have more THD20, so I've replaced the JFETs with BJTs and I've removed the voltage limiter cascode transistors. When I was testing the open loop gain I've noticed that gain peaking was occuring at a frequency near 10 MHz, I've tried to increase the value of the Miller compensation capacitor, but something strange happens, the phase raises at 10 MHz instead of decreasing. Attached is an amplifier that suffer from this problem, a bode plot of the open loop with 15 pF CMiller and with a 150 pF CMiller.

Best regards,
Daniel Almeida
Attached Images
File Type: jpg amp1.jpg (85.4 KB, 77 views)
File Type: jpg amp1_gain_peaking.jpg (173.3 KB, 76 views)
File Type: jpg amp1_gain_peaking_higher_c_miller.jpg (183.4 KB, 77 views)
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Old 12th September 2013, 01:39 PM   #2
cbdb is offline cbdb  Canada
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look again
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Old 12th September 2013, 01:39 PM   #3
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Did you try a series of values and observe a coherent response, or only this 2 values?
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Old 12th September 2013, 02:16 PM   #4
danny92 is offline danny92  Portugal
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Thank you for replying

I'm sorry for not providing more responses for different CMiller values.
Attached open loop response with CMiller sweep from 15pF to 330pF with 15pF steps, it's also attached the LTSpice file.

Best regards,
Daniel Almeida
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File Type: jpg amp1_cmiller_sweep.jpg (187.8 KB, 66 views)
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File Type: asc Amp8_6_bjt_input.asc (12.7 KB, 5 views)
File Type: txt Cordell Models.txt (11.4 KB, 1 views)
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Old 12th September 2013, 02:32 PM   #5
danny92 is offline danny92  Portugal
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I'm sorry, wrong LTSpice file, this one is correct.
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File Type: asc Amp8_6_bjt_input_wilson.asc (12.8 KB, 7 views)
File Type: txt Cordell Models.txt (11.4 KB, 1 views)
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Old 12th September 2013, 02:44 PM   #6
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Hi. Where did you pinch the "test lead" of the LT, after or before the inductance at the output?

Perhaps try removing it, with pure resistive loads it isn't needed.

In other hand I see the circuit too complex for the simple task it must to do.
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Old 12th September 2013, 03:38 PM   #7
danny92 is offline danny92  Portugal
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Hello and thanks for your reply,

The 1GH inductor is just to break the loop and to evaluate open loop response. The output probe is placed on Vout.
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Old 12th September 2013, 03:46 PM   #8
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Re-try removing it at all.
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Old 12th September 2013, 04:13 PM   #9
danny92 is offline danny92  Portugal
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Thanks for your reply,

I can try another way to break the loop like using a voltage source between Vout and the feedback resistor and then label this node for example a and then plot V(Vout)/V(a). But unfortunately the result is the same.

Best regards
Daniel Almeida
Attached Images
File Type: jpg amp1_cmiller_sweep_vout_a.jpg (188.5 KB, 47 views)
Attached Files
File Type: asc Amp8_6_bjt_input_wilson.asc (12.6 KB, 3 views)
File Type: txt Cordell Models.txt (11.4 KB, 0 views)
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Old 12th September 2013, 04:26 PM   #10
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I can suppose that the defect can be caused by a phase rotation in any other stage, but reflects there. Try put some low capacitances in other places in the circuit.

Don't forget that an amplifier with such a high gain is prone to self oscillate at high frequencies per se.

An in practice, or real world, things are worse, because simulators ignore stray capacitances and inductances present in all electronic component, including circuit traces.
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