Open loop gain peaking

[danny92]

Hi everyone,

I'm testing several IPS-VAS topologies based on Bob Cordell's designs, and I've noticed that the JFET input amps seem to have more THD20, so I've replaced the JFETs with BJTs and I've removed the voltage limiter cascode transistors. When I was testing the open loop gain I've noticed that gain peaking was occuring at a frequency near 10 MHz, I've tried to increase the value of the Miller compensation capacitor, but something strange happens, the phase raises at 10 MHz instead of decreasing. Attached is an amplifier that suffer from this problem, a bode plot of the open loop with 15 pF CMiller and with a 150 pF CMiller.

Best regards,
Daniel Almeida

 

[cbdb]

look again

 

[Osvaldo de Banfield]

Did you try a series of values and observe a coherent response, or only this 2 values?

 

[danny92]

Thank you for replying

I'm sorry for not providing more responses for different CMiller values.
Attached open loop response with CMiller sweep from 15pF to 330pF with 15pF steps, it's also attached the LTSpice file.

Best regards,
Daniel Almeida

 

[danny92]

I'm sorry, wrong LTSpice file, this one is correct.

 

[Osvaldo de Banfield]

Hi. Where did you pinch the "test lead" of the LT, after or before the inductance at the output?

Perhaps try removing it, with pure resistive loads it isn't needed.

In other hand I see the circuit too complex for the simple task it must to do.

 

[danny92]

Hello and thanks for your reply,

The 1GH inductor is just to break the loop and to evaluate open loop response. The output probe is placed on Vout.

 

[Osvaldo de Banfield]

Re-try removing it at all.

 

[danny92]

Thanks for your reply,

I can try another way to break the loop like using a voltage source between Vout and the feedback resistor and then label this node for example a and then plot V(Vout)/V(a). But unfortunately the result is the same.

Best regards
Daniel Almeida

 

[Osvaldo de Banfield]

I can suppose that the defect can be caused by a phase rotation in any other stage, but reflects there. Try put some low capacitances in other places in the circuit.

Don't forget that an amplifier with such a high gain is prone to self oscillate at high frequencies per se.

An in practice, or real world, things are worse, because simulators ignore stray capacitances and inductances present in all electronic component, including circuit traces.

 

[danny92]

Thank you Osvaldo,

Do you think that this peaking could cause real world problems?
In the closed loop step response I can't notice anything.
What I should do to avoid the oscilations?
I should try TMC, TPC or IMC?

Best regards,
Daniel Almeida

 

[Osvaldo de Banfield]

Sure. Although I can't understand such acronyms, but in my experience, any unstable amplifier becomes more unstable under feedback closed loop, as at some frequencies the NFB can rotate to positive making an uncontrolled oscillator, including the possibility of blown the entire power stage.

As an example, very different from it, I can show you an own design using tubes.

See photos 1 and 2. The circuit layout and the last, the schematic. See the capacitors labelled C9 and C10, they are the mica trimmers in the real circuit.

They are intended to neutralize the amplifier. It is a concept I took from RF circuitry. It consists of carrying a signal of equal amount from one circuit to other but 180 deg out of phase, so counteract the Miller capacitance.

See the oscillograms of the true circuit the behaviour as the capacitors are increasing capacitor's value, the signal is 1KHz not limited inside the amplifier. Look how entire amplifier starts to oscillate at its own frequency when the capacitor are over-adjusted.

By this reason I suggest to try many capacitors in your circuit. When running my simulation after doing true circuit, the amp oscillates with 9.4 pf for both caps (C9 and C10) and very undercompensated for 9pf, a variation of only .4pF‼. Surely I could neglect if not doing the true circuit. Note no negative feedback at all, in fact a small positive FB from WCF to the cascode amplifier to increase gain. If overcompensated, it oscillates at open loop, imagine it in a close loop. Disastrous.

Enjoy simulations, but real world is different.

Osvaldo.

 

[danny92]

Hi Osvaldo,

This seems to work but that's strange I've never saw that in other amplifiers.
LTSpice circuit and open and closed loop response attached.

Best regards,
Daniel Almeida

 

[danny92]

Sorry that's a problem with the closed loop response picture.

 

[Osvaldo de Banfield]

Yes, more or less what I said. Stabilize the amp before closing the loop. Too many signal stages causes each one of them increasing the phase rotation up to the point it becomes entirely unstable or oscillates.

 

[dadod]

Hi Osvaldo,

This seems to work but that's strange I've never saw that in other amplifiers.
LTSpice circuit and open and closed loop response attached.

Best regards,
Daniel Almeida

First you have to plot the loop gain.
Here with 15pF of the compensation caps and compensation of Q9 and Q10(drivers) it is perfectly stable with good PHM and GM. The peacking is comming from the triple output stage and it's good to use base stoppers for output transistors too, triple is known to be quite unstable if not tamed.

 

[danny92]

Hello dadod and thank you very much for your help,

I've added a Miller compensation capacitor on the inverting side of the differential amplifier used in the VAS, Bob Cordell's circuit only shows one in the non inverting side.
Adding this capacitor the amplifier seems a little more stable, why?

Best regards,
Daniel Almeida

 

[dadod]

Hello dadod and thank you very much for your help,

I've added a Miller compensation capacitor on the inverting side of the differential amplifier used in the VAS, Bob Cordell's circuit only shows one in the non inverting side.
Adding this capacitor the amplifier seems a little more stable, why?

Best regards,
Daniel Almeida

Just simulate and see. More Phase Margin and more Gain Margin more stabe.
BR Damir

 

[danny92]

Right, thank you for your help.