Miller Compensation Thread

[Zero D]

I'm sure i'm not the only one who's noticed various discussions "etc" taking place in other threads. Threads can easily evovle in ways they wern't initially intended, for all sorts of reasons. So i thought it'd be better if we could have a dedicated one of it's own. It also avoids highjacking other peoples threads.

Here's a few links to start off with, which although they mention CMOS IC's, "appear" to incorporate some interesting solutions. I couldn't view them, as i'm not a member of the IEE, but i expect some of you are, & could therefore hopefully shed some further light on the subject.

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A two-stage amplifier with active miller compensation

A two-stage amplifier with active miller compensation is presented in this paper. Unlike the two-stage amplifier with conventional miller compensation, the proposed structure doesn't contain right half plane zero. What is more, a left half plane zero is created to cancel the first non-dominant pole. The proposed structure improves the bandwidth significantly and reduces the dimension of the compensation capacitor. The proposed two-stage amplifier is designed and simulated in standard 0.6 ?m CMOS process. Simulation results show that the unit-gain frequency is increased by 9.4 times with only 38% increase in power consumption. The overall FoM is improved by 31.5 times.

https://ieeexplore.ieee.org/xpl/log...re.ieee.org/xpls/abs_all.jsp?arnumber=5967452

Design guidelines for reversed nested Miller compensation in three-stage amplifiers

The reversed nested Miller compensation technique applied to a three-stage operational amplifier is discussed in this paper and new and simple design equations, accurately predicting the loop-gain phase margin, are developed. Techniques for parasitic positive-zero cancellation are also investigated and compared. For this purpose, we found that using ing resistors is unpractical. Instead, exploiting only one follower (either a voltage or a current one) in the compensation branch results to be more appropriate. Indeed, not only does it avoid any additional constraint on stage transconductance, but it also overcomes the inherent limitations incurred by voltage and current followers when used to compensate two-stage amplifiers. Post-layout simulations on a CMOS opamp using the parameters of a 0.35-?m process are found to be in good agreement with the expected results.

https://ieeexplore.ieee.org/xpl/log...re.ieee.org/xpls/abs_all.jsp?arnumber=1198363

Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers

Several Miller compensation schemes using a current buffer in series with the compensation capacitor to modify the right-half-plane zero in fully differential two-stage CMOS operational amplifiers are analyzed. One scheme uses a current mirror as a current buffer, while the rest use a common-gate transistor as a current buffer. The gain transfer functions are derived for each topology, and approximate transfer-function coefficients are found that allow accurate estimation of the zero(s) and poles.

https://ieeexplore.ieee.org/xpl/log.../ieeexplore.ieee.org/iel5/8919/28337/01266829

 

[Dave Zan]

There is a lot of literature on compensation of CMOS amps.
The RHP zero is a major issue because of the low transconductance of MOSFETs. Much less of an issue for a typical bipolar VAS audio amplifier.
There are several theses on-line that are public access.
Educational but of limited relevance.

Best wishes
David.

 

[Walkalone]

Is this Miller caps secondary IPS like Bod Cordell's book
said?!

 

[Zero D]

Originally Posted by Dave Zan

Educational but of limited relevance

OK, but they were just for starters

@ Walkalone

Not sure, but somebody on here must know, you might think ?