I have conceived an idea (probably not new at all). Would like to create some transistor (TOxxx) style symbols for LTspice. Where these match the real life pin outs of the transistors and have the same outlines as a PCB silkscreen would be.
These symbols would function just the same as a normal transistor LTSpice symbol.
Have had a look around and can't find any and to be honest can't believe that this hasn't been done before. I think it would be good to allow better modelling of a PCB layout before prototype. It would also allow better visualisation between pcb layout and parasitic modelling.
Does anybody know of anything in existence already? Also, is there an idiots guide that anybody knows of for doing this? Can find stuff relating to sub circuits but not to this.
Please remember I'm simple of mind.
Paul
These symbols would function just the same as a normal transistor LTSpice symbol.
Have had a look around and can't find any and to be honest can't believe that this hasn't been done before. I think it would be good to allow better modelling of a PCB layout before prototype. It would also allow better visualisation between pcb layout and parasitic modelling.
Does anybody know of anything in existence already? Also, is there an idiots guide that anybody knows of for doing this? Can find stuff relating to sub circuits but not to this.
Please remember I'm simple of mind.
Paul
Bad idea. No one else would be able to read your diagrams. After a week away from it, you would not be able to read your own diagrams.
The symbol used to represent a bipolar transistor in a circuit diagram has 2 alternatives, NPN and PNP which are called according to the part number in a 1 to 1 relationship. The circuit diagram is specifically about understanding the electrical characteristics and communicating these precisely in a predictable "language". It does not care (generally) about physical variations.
The pcb on the other hand is about physical variations and one transistor may have many different package outlines (formed leads, straight leads, vertical mount, horizontal mount etc).
Some people do include the name of the package outline and other information on a circuit diagram but they always use the same transistor symbol.
The symbol used to represent a bipolar transistor in a circuit diagram has 2 alternatives, NPN and PNP which are called according to the part number in a 1 to 1 relationship. The circuit diagram is specifically about understanding the electrical characteristics and communicating these precisely in a predictable "language". It does not care (generally) about physical variations.
The pcb on the other hand is about physical variations and one transistor may have many different package outlines (formed leads, straight leads, vertical mount, horizontal mount etc).
Some people do include the name of the package outline and other information on a circuit diagram but they always use the same transistor symbol.
This is the process I'm starting at present.
I have an LTspice schematic less the parasistics, I also have a potential PCB layout. Looking for an easy way of representing this in LTspice to allow parasitics to be added in. My thinking was that if I had the different packages for the transistors in a PCB layout form I could copy the layout back from the PCB to LTspice exactly. Then any changes required in LTspice could then be transferred to the PCB layout accurately / exactly.
My first attempt at this ended up as a mass of lines crossing each other and was becoming a confusing mess.
I understand what you are saying about other people not understanding it but I would have the advantage of having the PCB layout.
It would also provide a good double checking process.
I have an LTspice schematic less the parasistics, I also have a potential PCB layout. Looking for an easy way of representing this in LTspice to allow parasitics to be added in. My thinking was that if I had the different packages for the transistors in a PCB layout form I could copy the layout back from the PCB to LTspice exactly. Then any changes required in LTspice could then be transferred to the PCB layout accurately / exactly.
My first attempt at this ended up as a mass of lines crossing each other and was becoming a confusing mess.
I understand what you are saying about other people not understanding it but I would have the advantage of having the PCB layout.
It would also provide a good double checking process.
No, simple resistor/capacitor/inductor elements. Harder to model electromagnetic coupling. Point to note is that spice modelling is a simplistic partial solution most of the time. All designs should be bread-boarded.
There are also conventions that should be followed in pcb design that minimise parasitic effects. Star grounds, fat traces, appropriate separation, decoupling caps, thermal isolation and the list goes on. Most of this comes with experience, not Spice.
There are some good threads here on pcb layout that you should be reading too.
There are also conventions that should be followed in pcb design that minimise parasitic effects. Star grounds, fat traces, appropriate separation, decoupling caps, thermal isolation and the list goes on. Most of this comes with experience, not Spice.
There are some good threads here on pcb layout that you should be reading too.
Decoupling caps is one thing that my first attempt at parasistics taught me about. Learnt that the standard values you see like the 100nF films don't necessarily work as you expect and that snubbers are required. Also, that the positioning of the caps is critical. I recall doing the output stage and found that the rails were ringing massively. I know that LTspice is limited but some parsitics is better than none. A simulation with no parasistics with perfect conductors is much further away from reality than one with an attempt at parasistics.
But I know you're right reality trumps simulation everytime and that real life experience is essential. Something I am sadly lacking in.
Have found a few decent threads on PCB layout and have read about loop area / length as well. Electromagnetic coupling... I think I'll discover about that during prototyping.
But I know you're right reality trumps simulation everytime and that real life experience is essential. Something I am sadly lacking in.
Have found a few decent threads on PCB layout and have read about loop area / length as well. Electromagnetic coupling... I think I'll discover about that during prototyping.
The LTSpice "capacitor" and "inductor" components are actually generalized impedances. They include provisions for first-order, linear, parasitic elements such as series inductance, leakage resistance, etc. Look up "capacitor" and "inductor" the LTSpice "Help" file. (Note that the LTSpice capacitor component includes enough optional parasitic elements that it can stand-in as a reasonable first-order model for a quartz crystal!)
Some manufacturers publish Data Sheets with enough information that you can make reasonable guesses at the values of component parasitics. Including the effective parasitic elements arising from physical PWB layouts is at least an order of magnitude more difficult - not because SPICE can't model them, but because the designer is very hard pressed to determine reasonable values.
This parasitic element feature is seldom used when you draw a schematic diagram and simply assign values, but if you use the "Select Capacitor" dialog rather than just entering numbers, you will find a library of commercial parts with at least a typical ESR specified.
Dale
You can certainly edit the parts and make a pictorial schematic, but I too think it's a bad idea. You'll just end up with more people who don't know how to draw a clear traditional schematic or won't be able to understand one.
I'm just now trying to convert something similar, an interconnected multi-wafer rotary switch schematic to something I can actually understand. PITA- schematics should reflect electrical operation, not physical implementation.
I'm just now trying to convert something similar, an interconnected multi-wafer rotary switch schematic to something I can actually understand. PITA- schematics should reflect electrical operation, not physical implementation.
It would appear my idea is less than popular...
I agree if the purpose it to convey an idea. I'm more interested in using it as a design tool. The drawings will almost certainly never make it out of my computer. Definitely, for the communication of a design a plain standard schematic using standard symbols should be used. It is the accepted way.
I seems a lot easier to me to work back from a potential prototype PCB layout into a pictorial Ltspice version. Then if you get problems with parasitics in LTspice any changes will be easier to work into that prototype PCB layout.
The PCB I want to do parasitic simulation on isn't even close to the schematic in layout. For example, the power rails in the schematic run top and bottom but in the PCB they run down the centre.
Maybe my brain is just strange (and stubborn).
I agree if the purpose it to convey an idea. I'm more interested in using it as a design tool. The drawings will almost certainly never make it out of my computer. Definitely, for the communication of a design a plain standard schematic using standard symbols should be used. It is the accepted way.
I seems a lot easier to me to work back from a potential prototype PCB layout into a pictorial Ltspice version. Then if you get problems with parasitics in LTspice any changes will be easier to work into that prototype PCB layout.
The PCB I want to do parasitic simulation on isn't even close to the schematic in layout. For example, the power rails in the schematic run top and bottom but in the PCB they run down the centre.
Maybe my brain is just strange (and stubborn).
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This does bring to mind the idea of a physical design tool like a combination of mechanical 3D CAD and Spice. Maybe the RF or IC design world has such things. You'd add in the parasitics and gauge the effect. IMO, the problem is knowing where all the possible parasitics are. Component bodies to nearby traces, transistor collectors to heatsinks through the insulators, wire bundles, routing that forms large current loops instead of small and who knows what else. I suppose just like a PCB program, there'd be a component model, but it would take into account surface area and strays. For the moment it seems easiest to just incorporate the expected strays in the regular Spice and maybe label them "strays".
Yes, there are ecad packages that do most of the parasitics and electromagnetics of the board and copper more-or-less automatically. Usually very expensive.
And if you go to the Cornell-Dubilier website they have a java applet that will create a frequency-dependent and temperature-dependent spice capacitor model for any of their electrolytics.
And if you go to the Cornell-Dubilier website they have a java applet that will create a frequency-dependent and temperature-dependent spice capacitor model for any of their electrolytics.
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As good as LTspice is for simulation, using it to produce netlists for PCB design programs such as FreePCB is a bit of a pain. For one, you have to make up your own symbols and subcircuit files for transistors to get the pin order right. Here is a good article on how to do it:
Using LTspice With FreePCB
Although it works well, I can't shake the feeling that it might be easier to just redraw the schematic into an integrated design tool such as DesignSpark.
Using LTspice With FreePCB
Although it works well, I can't shake the feeling that it might be easier to just redraw the schematic into an integrated design tool such as DesignSpark.
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