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Old 1st July 2013, 09:09 PM   #21
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Quote:
Originally Posted by PMI View Post
I was told once that relying on square waves leads to pushing the envelope too far in favor of a wide bandwidth v. a noise free circuit, but everyone is still doing it...
Aaw too true, there's gotta be a balance!

I've now prepared the schematic. It's large and most likely will not fit full-screen. You'll have to save it to your computer and view it unzoomed. The probe baloons show currents and voltage in the idle state. Component values are exactly as they are on the real prototype except for the transistors - they're all BC550C/560C. These were not available in the sim.

I'll follow up with a thorough explanation on its workings soon

May be an interesting thing to note is that it is a VFB circuit, there's no CFB at all.
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Last edited by MagicBox; 1st July 2013 at 09:12 PM.
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Old 1st July 2013, 10:05 PM   #22
Zero D is offline Zero D  United Kingdom
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@ MagicBox

Yeah the image is too big to save in full Minor detail in the screenie

What software is your simmer ? The virtual instruments look the same as in my Multisim.
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Old 2nd July 2013, 05:56 AM   #23
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It's an older version of Multisim yes, version 9.

I want to note though that it is more of a conceptional circuit. There's no output snubber etc, the outputstage is the A1 unity gain block. Today I'll write up how it works.
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Old 2nd July 2013, 10:27 AM   #24
Zero D is offline Zero D  United Kingdom
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@ MagicBox

Yes i thought it was MS, apart from the VI's, MS creates a MUCH neater layout than MOST LtSpice designs that appear on here, & elsewhere

Looking forward to your write up
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Old 2nd July 2013, 03:54 PM   #25
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Well, are you guys ready for a book? *grins*

Here's the explanation as promised

The Basics

Under normal idle conditions, the VAS current is supposed to be a stable DC current. This means, both the N and P VAS devices conduct the same amount of current, keeping the output centered. When the input changes, the VAS action is to open up one device, while closing the other untill the output settles to the new value. This is commonly descibed as a push-pull action. The current variations in the VAS rail represent the error signal of the feedback system. Generally we can say that the current through the VAS devices will be a constant. This is the principle that is used to create and implement the auto-bias function of this VAS.

Where to start?

The easiest way to understand this circuit is remembering the mentioned principle while we start at the cascode devices Q9 and Q20 and work our way to the input of this VAS. We will assume a steady state VAS current of about 12mA. It's the cascode Q9 and Q20 that convert the current to a voltage. Devices Q4 and Q24 are the cascoded devices. They are responsible for the actual push-pull action applied to the VAS current.

Autobias

In order to autobias our desired VAS current, we will need a way to perform 3 tasks: Measure. Compare. Control. We need to measure the VAS current, compare it to a reference, and either increase or decrease the VAS current. Measuring and comparing is done by the components on top of the schematic. We have Q7, Q8, Q17, Q18 forming differential pair with a push-pull output. We have a sense resistor R10 and we have D3 providing us with a 0.7V reference. Q6 and R5 form a CCS for the diff. pair of about 250uA. R9 and R2 are a low-pass filter to remove most of the HF error signals that develop over R10. Q5 and R4 is an 1mA CCS. This current source plays an important role. It provides us with a current rail that can fit the voltage reference (D3) and it will always flow, through the cascodes, into the opposite 1mA CCS Q21 and R32. This means, that even if the VAS devices are both off (zero state), the voltage reference is working and causing its voltage drop. Secondly the 1mA current passing through the cascodes allows them to bias properly without their emitters going towards their respective supply rails, crippling operation of the comparator. At startup there is no VAS current, so there won't be a voltage drop across R10. The comparator will then signal to increase the VAS current. And so we get at the 3rd task:

Current Control

The VAS current is controlled by a group of 4 transistors, Q10, Q11, Q15 and Q16. These are arranged such that two current rails are created. One going from V+ through Q10, R13, Q16 and into Q23 which forms a current mirror with the VAS device Q24. The other rail going from GND through Q15, R14, Q11 into Q3 which forms the N side current mirror with Q4. The current through these legs is controlled by a voltage applied between the bases of Q11 and Q16 and the input signal (bases of Q10 and Q15). Assuming the input voltage sits halfway between the applied bias voltage across C4 + C12, the currents in both legs will be equal (I = (0.5*Vbias - 2*Vbe) / Re). The bias voltage is determined by the output of the comparator which charges/discharges C4 which acts as an integrator. Once the voltage drop across R10 equals D3's drop the comparator output will settle and keep the voltage across C4 stable.

Gain

The VAS devices traditionally also provide the stage gain. This is not the case in this design. Instead, the VAS current is mirrored, leaving us with a current gain of 1. This means Q4 and Q24 are no longer responsible for gain. Instead, the gain comes from the four control transistors Q10, Q11, Q15, Q16. The mid point where the bases of Q10 and A15 are connected is a high impedance input and is relative to the external voltage applied between the bases of Q11 and Q16. When the input is modulated, current in one input leg will rise while it will drop in the other. These currents are then mirrored resulting in simmetrical push-pull action. Since the amp's negative feedback seeks to remove the error signal, we can then deduct it seeks to keep the standing VAS current. We can then deduct that the IPS output will try to idle the VAS input such that the mirror output device's conductivity is just right to have the VAS output where it needs to be to remove the feedback error. This happens to be halfway the applied bias voltage. Thus, halfway the voltage across C4 + C12. The 10V zener D5 is nothing but a voltage offset for the applied bias voltage. This way we can control at which voltage level the VAS input sits when idle. With this, we control at which voltage the output of the IPS will settle and as such, locate it somehwere to optimize Vds across the input devices of the IPS. This is the flexibility gained by using current mirrors for the VAS current; voltage meaning and distribution across the input legs is completely unrestricted since the mirrors are current inputs and no voltage inputs.

Compensation

There are two compensation capacitors. The Cdom caps C3 and C9. But there's also a not so obvious capacitor, which is the 15pF C6. This capacitor can be very low in value but it's still essential. It's best seen as a compensation cap one usually places between an opamp's output and inverting input. In fact, that is what the VAS input is, an inverting input. Because the mirrors have a very small propagation delay, the stage is very vast and as such can do with a low capacitance. Without it, however the circuit really malforms the wave it tries to produce.

Conclusion

The schematic consists of basic buildingblocks. The main points of the topology are the current mirrors, which then allow for VAS upper and lower currents to be controlled in a push-pull fashion using a 4-transistor gain block. This also provides VAS input symmetry because each leg containes one N and P tranny, thus cumulative behaviour in both legs is identical unlike with common VAS devices stuck to supply rails that also act as gain devices. In this circuit the current gain is 1 in the mirrors, so the N/P difference for the pairs is not amplified by gain. And as said before, the VAS reference input voltage can be freely chosen to optimize the IPS output voltage.

The nice thing is that one aspect keeps leading to another, barely using any more components, ending up with a little circuit that works in an (I think) optimal synergy. It's a reasonably simple schematic, barely as large as some of the amps I see on DIY and yet I think it's the topology's synergy that results in this performance. In the sim I achieved sub ppm at 500W full power at one time. While unrealistic, the results were consistent for the topology. I've built it at various power scales and no matter the scale, it will have consistently low THD at max output levels.

I'm certainly going to develop it further; there are still things to be done. One of them is to limit VAS input currents when the input is overdriven. This I could do by inserting JFETs between the power rails and Q10 / Q15 that would have an Idss of about twice the intended VAS standing current. Or implement CCSes of twice the VAS current. Then it will still allow for a powerful error signal and keeping things in check while the VAS currents will never exceed their set maximum.

Well. I think I've written down a whole book but I hope I was clear enough in my explanations If you have questions, just ask..
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Last edited by MagicBox; 2nd July 2013 at 04:02 PM.
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Old 2nd July 2013, 06:09 PM   #26
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I made it too hard to understand? Or is everyone laughing and pointing fingers at my ways of thinking?
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Old 2nd July 2013, 06:31 PM   #27
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one question whilst I ponder over more things: what is the output voltage swing with the PSU you are using - that is, will your design work best with rails higher than the output current followers? Mik
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Old 2nd July 2013, 06:46 PM   #28
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I would recommend powering the IPS/VAS with a dedicated regulated supply indeed. The output swing (per suppy half) is Vsupply - 5.1v - ~ 7.5v Vce headroom at your desired max power. When the output signal pushes the collectors of the cascodes to under 7V with respect to the emitters, distortion begins to increase proportionally untill clipping. Keeping about 7.5V headroom keeps it all peachy distortion wise. Also have to take into account Vbe/gs drop of the output devices.

The supply rails can get rather high in relation to the actual output swing, but the IPS/VAS stages hardly require current so inspite the high voltages, the regulated supplies don't take much in terms of power handling. +45V/-45V rails would comfortably do about 120W into 4 ohms with still some VAS output headroom left.

For the prototype I used relatively low voltages and the lab PSU's current limiters to guard for disasters during assembly and test. So far I only had some resistor smoke but no bust trannies
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Old 2nd July 2013, 10:59 PM   #29
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Hi Magicbox, Ive seen a very similar circuit before, or lets say the concept of it. It is used by Analog devices in ICs such as AD8011. Ill have to study your circuit to see if any advantages are gained.
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Old 3rd July 2013, 08:36 PM   #30
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Thanks, I'll be curious to hear any findings

Meanwhile I've been working on clipping and saturation behaviour. I had to make a small change to the way the biassing works in order for the added shunt clamps to work accurately. Now the VAS input currents can never exceed a certain value, set to approximately 2 times the desired VAS current. The VAS output currents are mirrors of the inputs and hence will be protected against over-current. The clamps are such that neither VAS input leg would cut off completely. This keeps the entire VAS unsaturated even during input stage overdrive There's no more saturation locking taking place under some conditions either.

So, now it acts very well behaved under sustained clipping/overdrive as well. These bits were really needed to make the VAS complete and reliable under all conditions.
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