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Old 13th July 2013, 07:35 PM   #141
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I usually don't do anything with Rpar. It would be useful if you want to be able to leave a cap dangling without convergence problems.
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Old 13th July 2013, 07:41 PM   #142
gootee is offline gootee  United States
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I think that in order to disable the Rpar and Cpar of capacitors, you have to explicitly set them to zero. Otherwise, I think they have some default value.

But for Rpar of electrolytic caps, the manufacturer often gives something like:

"LEAKAGE CURRENT: 0.01CV, or 3uA, whichever is greater.".

So that means i = 0.01CV. But R = V/I. So Rpar = 1/(0.01C). C is in Farads.

----

For your slowness and convergence problems, the first thing I usually try is switching to the other solver, either normal or alternate, whichever one I wasn't using.

The second thing I try is reducing the time-step value. If you are setting the frequency of the input with a param statement, set the time step with something like {1/(5000*freq)}. If you see lots of spiky "glitches", often it means that the time-step is too large. (Unfortunately, you want it as large as it can be, to make the sim run faster. But you also want it as small as possible to make it more accurate. Like a lot of things, if you adjust it downward until the results stop changing, it should be good.)

One big gotcha can be high frequency resonances. Sometimes you can get runtime speeds of femtoseconds per second, if it converges at all! To defeat that behavior, you can try to make sure that everything has SOME resistance (for damping), i.e. no caps or inductors without ESRs. Sometimes you might have to insert small resistances into every trace (1 to 100 Ohms), to see where it stops the ringing. ALSO, always RF-filter (low pass) the inputs (and maybe add small resistors to the PSU lines), et al, and DON'T use signals that have super-fast edge times, especially not ideal square waves with zero rise and fall times. And even with reasonable rise and fall times, you still should LP filter them, so the corners aren't perfectly sharp. Also, sometimes you might have to blindly try inserting filters or snubber/terminator resistors, just to get a handle on where there might be HF ringing. If you can get even just a short bit of a plot, you can start clicking on different nodes and magnify the hell out of the end of the plot to try to see where there might be HF ringing that's starting to bloom.

Another thing that I have had to change, a lot, is Gmin. Usually I lower it but sometimes I have to raise it. You can also change the other parameters there, such as Trtol. Once you find what works, put it in a comment on your schematic!

Also, I always turn off all compression.

If you haven't joined the LT-SPICE USERS GROUP at yahoogroups.com, now is the time...

Cheers,

Tom

Last edited by gootee; 13th July 2013 at 08:08 PM.
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Old 14th July 2013, 11:26 AM   #143
mcd99uk is offline mcd99uk  United Kingdom
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Thank you for the hints.

Progress, I think.

Reducing time step has brought my THD right back to the non parasitic values. Eg THD 20K = 0.000543%

Also changing Gmin to 2e-011 has stopped all source stepping.

Are the simulation results still valid?

Should I now go through with square wave inputs and check for ringing etc?

Man thanks

Paul

Last edited by mcd99uk; 14th July 2013 at 11:33 AM.
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Old 14th July 2013, 01:20 PM   #144
mcd99uk is offline mcd99uk  United Kingdom
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This parasitic stuff is very enlightening. I have had to change my compensation scheme to Edmonds DTMC which works very well. have changed the values and added back the RC network across the feedback resistor. Also, reintroduced the TIS emitter decoupling caps. End result has been a very clean closed loop plot, clean square waves and (I think impressive) PM = 104 degrees and GM = 20dB.

Gone is the AFEC as it made the THD worse with this alternative compensation.

Also, seen the need to improve the opamp PSU.

I would like to add some zeros to cancel some of the excess phase though. Not sure how to do this at present.

Last edited by mcd99uk; 14th July 2013 at 01:23 PM.
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Old 14th July 2013, 03:28 PM   #145
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Looks like you're running into the same as I am: trying to find an optimal tradeoff between stability and THD I haven't been able to widen the phase margin of my VAS without detoriating THD at the same time. Wouldn't it be nice if we could increase the gain slope without additional phase
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Old 14th July 2013, 03:33 PM   #146
mcd99uk is offline mcd99uk  United Kingdom
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Yes, its one of those triangular relationships Keantoken was on about. I noticed you were struggling with stability and THD with your VAS (which is beginning to make some sort of sense to me now you're adding output stages. There's no free lunch but there may be better value.

THD/Phase Margin/Gain Margin.

This is why I'm trying to understand how to use zeros to cancel out some of the poles. This may provide a way forward.
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Old 14th July 2013, 03:40 PM   #147
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You can try a HF snubber at the LTP output (I used 220p/5.6K) and lead it into the LTP tail. It pushed back phase in the mid HF band some, sacrificing a little THD.
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Old 14th July 2013, 03:59 PM   #148
mcd99uk is offline mcd99uk  United Kingdom
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If only i had a ULGF. I'm utilizing an X buffer style input stage.
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Old 14th July 2013, 04:54 PM   #149
mcd99uk is offline mcd99uk  United Kingdom
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Quote:
Originally Posted by mcd99uk View Post
If only i had a ULGF. I'm utilizing an X buffer style input stage.
That was supposed to have been LTP.
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Old 15th July 2013, 10:48 PM   #150
mcd99uk is offline mcd99uk  United Kingdom
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I would like to ask your opinion on this loop gain plot. This is from the full parasitic simulation. Would like your opinion on the shelving at around 200Mhz. Is this a problem?

The top line is the gain the bottom line is the group delay.

THD @ 20Khz is now 0.000200% (+/-35V out)
PM = 100 degrees / GM = 16dB.

Many thanks

Paul
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