PeeCeeBee

For the input ground reference, I think that is a good idea.

I have to think about the bias ground.

In some other applications I am familiar with, a ground trace which circles the board can (although not necessarily will) cause some issues which then have to be overcome in other ways. What I am referring to is that as the load shifts from one rail to the other, an alternating current is generated in what is essentially a loop, and a loop antenna. The current reverses direction when the output signal crosses zero. So if you bring a small signal on a pair of wires close to that without additional shielding, there may be an issue. (note that I say "may", not will).

So splitting the ground trace in whatever way would help with that too, I think.

Once the caps after the diodes are charged the total AC current in the onboard ground traces will be very small as the speaker return will go to the star ground and not on-board ground. Still, this very small AC can cause great problems with the perfect combination of C and L and damping the L is what the two 10R will do. I think input bias current will not face any problem and RF suppression through 100pF won't be significantly affected either as total resistance from input 0V to ground will be ~5R.
 
Once the caps after the diodes are charged the total AC current in the onboard ground traces will be very small as the speaker return will go to the star ground and not on-board ground. Still, this very small AC can cause great problems with the perfect combination of C and L and damping the L is what the two 10R will do. I think input bias current will not face any problem and RF suppression through 100pF won't be significantly affected either as total resistance from input 0V to ground will be ~5R.
Make sense.

I would still like to understand what is taking place at the diode which splits the rails... did you read my last post on that?
 
I would still like to understand what is taking place at the diode which splits the rails... did you read my last post on that?

Yes. Replied in post 839((mistype)read below :p). :)

The holes for the elcos and diodes will be made 1mm. Also the VAS and FET holes will be appropriately enlarged when finalizing the layout. It currently looks like the attachment below.

edit: the VAS heatsink can't be in touch with the board. I can't move the diodes anywhere without significantly increasing board width.
 

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Don't think this should be an audible problem even w/o the new power supply. Not if you are using the same on-board caps I am.

If I remember correctly, by the time I switched to a conventional 3x4700uF configuration with CRC or CLCRC, that diode was always on at power levels that correspond to normal listening volume.

@Shaan, correct me if I am wrong, I can check this again.

Sorry, missed it completely! :headbash:

I think all we need is a bigger transformer and bigger filter caps, meaning better regulation; plus some form of resistive or inductive PS ripple atennuation, in order to make sure the diode is never turned off. We need a power low-pass filter. :D

As much as I can understand, the PS sawtooth may have some effect on the diode turn-off, and the filtering removes it from supply, rendering the diode unnecessary. With CRC/CLCRC this may well be true, but I can't test it myself. Some scope shot will be helpful.

I am, however, leaving the on-board dioded as-is. If not necessary we can just short the pads.

:)

edit: any comment on the layout? can we publish the pdf?
 
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I will try to post the pics later tonight, or tomorrow.

I am not suggesting to remove the series diode permanently, but perhaps to test without it once or twice, to see what happens.

Layout looks fine to me, but you may want to give it a day so others can comment.

I do not know what track-to-track spacing needs to be for a self-etched board. Under-etch might make a couple spots close, not sure. For example the track which connects the two gate resistors on one side seems close to the ground trace.
 
I will try to post the pics later tonight, or tomorrow.

I am not suggesting to remove the series diode permanently, but perhaps to test without it once or twice, to see what happens.

Of course, DIY spirit. :up:

Layout looks fine to me, but you may want to give it a day so others can comment.

Sure. I am not planning to etch it currently. So fellows decide when it will be released. :)

I do not know what track-to-track spacing needs to be for a self-etched board. Under-etch might make a couple spots close, not sure. For example the track which connects the two gate resistors on one side seems close to the ground trace.

Thanks for noting. Will be repaired.
 
Lateral Mosfets with high RdsON do not ensure even current sharing unless tightly matched; hence, Source resistors will benefit.

There will be uneven current sharing with unmatched LatMos, but with them it is not a question of survival as is with BJT, so LatMos can in fact be used without source resisitors, especially where small pcb size is imperative.
 
Easy Paralleling

To whom it may concern, from Ben Duncan's "High Performance Amplifiers", quote:

Mosfets transition from positive, through zero, into negative temperature coefficient of gate treshold voltage ultimately forces balanced sharing. In Lateral MOSFETs, the transition takes place at such low currents (below 200mA, compared to typically 2 Amperes and above for D-Mosfets (vertical)) that these types can be simply paralleled without any ballast resistors, or even selection, particularly when the FETsa re mutually well thermally coupled. A prime examples are double die MOSFETS.

Because D-MOS switching Mosfets (vertical) have a temperature coefficient that changes from positive and thus suicidal (like BJTs), to being negative and thus self-protecting, at a current that will cause substantial dissipation (2A x 100v = 200W), the paralleling of switching MOSFETS requires individual Vgs and even conductance matching at a high percentage of rated drain current, and ideally also ballast resisitors in line with each source leg. This rather deflates the D-MOS's great benefit over L-MOS, of lower cost due to large volume industrial use.
 
VSSA/PCB/layout by PMI modules

"Modules" are finished. Electrolitics are all Panasonic FR (two 1000uF and one 2200uF). The most important deviation from LC's circuit are that instead of 10uF MKT in the feedback circuit I used Philips 1uF Polycarbonate (these are hard to find because no longer in production for more than decade). Polycarbonate is famous for it's non plus ultra slew rate characteristics. This is not a big deal, circuit will work properly with only 2200uF and no film caps at all.

Heatsinks may seem too small but for my small listening room and high efficiency loudspeakers this is enough. Most of the dissipation will be quiescent so for the time being they will do. I do not expect problems with these 1,5K/W heatsinks.
 

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Dear Shaan,
What will be the arrangement for the Main Heat sinks? The mounting of Laterals on them may not be symmetric and optimal.
--g annaji.

Hi annaji.

Are you talking about the double output version? The board is 2" x 4.5", preferably full board mounted on heatsink, like the attachments above in ivan's post. The problem is that this kind of PCBs doesn't allow thermally perfect symmetric FET mount. :(
 
@IvanLukic: Looks great (well, I am a bit biased... :D)

If anything, the boards look cleaner than mine with the fastons in place than the big green screw-terminals I am using for testing, and the spacing around the cap in the Zobel network looks more correct on your board.

edit:

check the temperature of the main heatsink after you set it up. At 150 ma bias current and 35-37V rail voltage, I measured a 10-12C temperature rise above room temps, using a heatsink rated at 0.65 C/watt. At the small VAS heatsinks, I measured around 20-25C above room temperature. As the temperature rises, the VAS bias current changes a bit, so if you are planning on a "warm" VSSA build, you have to make a decision on when (what temperature) to set the VAS bias.
 
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...The problem is that this kind of PCBs doesn't allow thermally perfect symmetric FET mount. :(
If properly mounted, this will make only a tiny difference (tested and measured). Should not be an issue with mosfets at all, IMO. ... would be a bit more important w. BJT's though.

How you attach the four devices to the heatsink presents a much bigger challenge in the case of diy, at least for me. That is the case regardless of the layout, and made more critical by small boards with devices in two rows, and heatsinks that may not be perfectly smooth and level, and if pins just "happen" to be soldered before the boards are mounted to the heatsink, and, and... (ok, I will stop now, :D)

:magnify:... At some point you may want to post some directions on the correct steps to align, mount, and solder two rows of devices...