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Old 5th July 2013, 05:13 PM   #841
shaan is offline shaan  India
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Quote:
Originally Posted by PMI View Post
For the input ground reference, I think that is a good idea.

I have to think about the bias ground.

In some other applications I am familiar with, a ground trace which circles the board can (although not necessarily will) cause some issues which then have to be overcome in other ways. What I am referring to is that as the load shifts from one rail to the other, an alternating current is generated in what is essentially a loop, and a loop antenna. The current reverses direction when the output signal crosses zero. So if you bring a small signal on a pair of wires close to that without additional shielding, there may be an issue. (note that I say "may", not will).

So splitting the ground trace in whatever way would help with that too, I think.
Once the caps after the diodes are charged the total AC current in the onboard ground traces will be very small as the speaker return will go to the star ground and not on-board ground. Still, this very small AC can cause great problems with the perfect combination of C and L and damping the L is what the two 10R will do. I think input bias current will not face any problem and RF suppression through 100pF won't be significantly affected either as total resistance from input 0V to ground will be ~5R.
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Old 5th July 2013, 05:46 PM   #842
PMI is offline PMI  United States
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Quote:
Originally Posted by shaan View Post
Once the caps after the diodes are charged the total AC current in the onboard ground traces will be very small as the speaker return will go to the star ground and not on-board ground. Still, this very small AC can cause great problems with the perfect combination of C and L and damping the L is what the two 10R will do. I think input bias current will not face any problem and RF suppression through 100pF won't be significantly affected either as total resistance from input 0V to ground will be ~5R.
Make sense.

I would still like to understand what is taking place at the diode which splits the rails... did you read my last post on that?
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Old 5th July 2013, 07:14 PM   #843
shaan is offline shaan  India
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Originally Posted by PMI View Post
I would still like to understand what is taking place at the diode which splits the rails... did you read my last post on that?
Yes. Replied in post 839((mistype)read below ).

The holes for the elcos and diodes will be made 1mm. Also the VAS and FET holes will be appropriately enlarged when finalizing the layout. It currently looks like the attachment below.

edit: the VAS heatsink can't be in touch with the board. I can't move the diodes anywhere without significantly increasing board width.
Attached Images
File Type: png pcb_hp_full_draft.PNG (47.6 KB, 306 views)
File Type: png pcb_hp_lay_draft.PNG (27.1 KB, 304 views)

Last edited by shaan; 5th July 2013 at 07:27 PM. Reason: text missing
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Old 5th July 2013, 07:33 PM   #844
PMI is offline PMI  United States
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Originally Posted by shaan View Post
Yes. Replied in post 839((mistype)read below ).
Y, got that part. My post 801 when we were talking about the diodes earlier. (what can I say,... ) I can post a scope pic, IF I find it again (sigh)
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Old 5th July 2013, 07:46 PM   #845
shaan is offline shaan  India
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Originally Posted by PMI View Post
Don't think this should be an audible problem even w/o the new power supply. Not if you are using the same on-board caps I am.

If I remember correctly, by the time I switched to a conventional 3x4700uF configuration with CRC or CLCRC, that diode was always on at power levels that correspond to normal listening volume.

@Shaan, correct me if I am wrong, I can check this again.
Sorry, missed it completely!

I think all we need is a bigger transformer and bigger filter caps, meaning better regulation; plus some form of resistive or inductive PS ripple atennuation, in order to make sure the diode is never turned off. We need a power low-pass filter.

As much as I can understand, the PS sawtooth may have some effect on the diode turn-off, and the filtering removes it from supply, rendering the diode unnecessary. With CRC/CLCRC this may well be true, but I can't test it myself. Some scope shot will be helpful.

I am, however, leaving the on-board dioded as-is. If not necessary we can just short the pads.



edit: any comment on the layout? can we publish the pdf?

Last edited by shaan; 5th July 2013 at 07:51 PM.
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Old 5th July 2013, 08:47 PM   #846
PMI is offline PMI  United States
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I will try to post the pics later tonight, or tomorrow.

I am not suggesting to remove the series diode permanently, but perhaps to test without it once or twice, to see what happens.

Layout looks fine to me, but you may want to give it a day so others can comment.

I do not know what track-to-track spacing needs to be for a self-etched board. Under-etch might make a couple spots close, not sure. For example the track which connects the two gate resistors on one side seems close to the ground trace.
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Old 5th July 2013, 08:58 PM   #847
shaan is offline shaan  India
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Originally Posted by PMI View Post
I will try to post the pics later tonight, or tomorrow.

I am not suggesting to remove the series diode permanently, but perhaps to test without it once or twice, to see what happens.
Of course, DIY spirit.

Quote:
Layout looks fine to me, but you may want to give it a day so others can comment.
Sure. I am not planning to etch it currently. So fellows decide when it will be released.

Quote:
I do not know what track-to-track spacing needs to be for a self-etched board. Under-etch might make a couple spots close, not sure. For example the track which connects the two gate resistors on one side seems close to the ground trace.
Thanks for noting. Will be repaired.
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Old 6th July 2013, 02:41 AM   #848
gannaji is offline gannaji  India
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edit: any comment on the layout? can we publish the pdf?
Dear Shaan,
What will be the arrangement for the Main Heat sinks? The mounting of Laterals on them may not be symmetric and optimal.
--g annaji.
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Old 6th July 2013, 03:04 AM   #849
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Lateral Mosfets with high RdsON do not ensure even current sharing unless tightly matched; hence, Source resistors will benefit.
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Old 6th July 2013, 04:05 AM   #850
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Originally Posted by Samuel Jayaraj View Post
Lateral Mosfets with high RdsON do not ensure even current sharing unless tightly matched; hence, Source resistors will benefit.
There will be uneven current sharing with unmatched LatMos, but with them it is not a question of survival as is with BJT, so LatMos can in fact be used without source resisitors, especially where small pcb size is imperative.
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