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Old 5th July 2013, 09:01 AM   #831
shaan is offline shaan  India
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Quote:
Originally Posted by borys View Post
Looks cool.
Thanks.

Quote:
...if you are using multiple pairs of outputs I would recommend source resistors anyway.
Why? The 1ohm RDSon of the laterals can't force current sharing? Besides, I'm afraid of putting inductive elements in the source node, can create mysterious problems.

Quote:
...by adding only 3 small elements per rail you are getting around 35W more - from the same psu.
Haven't tested this myself so it may be added to a later version of the board when I do. I would request fellows to try the config with bootstrap and laterals themselves before publishing a design for it.

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Old 5th July 2013, 09:05 AM   #832
shaan is offline shaan  India
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Hi Arif and khalsa.

Thanks for the kind words.
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Old 5th July 2013, 09:11 AM   #833
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Quote:
Originally Posted by shaan View Post
What is the lead spacing of the MKT?
Shaan,
I got 27.5mm lead spacing for same brand 1uF that u use...
this one 10uF/100v
on the right is the black one
but we can always use multiple holes
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Old 5th July 2013, 09:32 AM   #834
naf is offline naf  Indonesia
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Thanks Bli John,
I have 10uf/100 epcos and it likely 28mm,

@Shaan,
better to use multiple hole
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Old 5th July 2013, 09:55 AM   #835
wiljj78 is offline wiljj78  Philippines
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EPCOS datasheet say's for 10uf
W x H x L
Dim: 9.0 X 17.5 X 18.0 mm - Pitch 15.0mm @ 63VDC
Dim: 10.5 X 18.5 X 26.5 mm - Pitch 22.5mm @ 63VDC & 100VDC
Dim: 11.0 X 21.0 X 31.5 mm - Pitch 27.5mm @ 63VDC & 100VDC

Max dim w/ Multi hole is better way to go....

Last edited by wiljj78; 5th July 2013 at 09:59 AM.
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Old 5th July 2013, 11:08 AM   #836
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Originally Posted by wiljj78 View Post
Max dim w/ Multi hole is better way to go....
Absolutely!
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Old 5th July 2013, 12:02 PM   #837
borys is offline borys  Poland
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shaan
Thanks for explaining, if rdson is around 1r will be fine.
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Old 5th July 2013, 01:12 PM   #838
PMI is offline PMI  United States
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@shaan: Some component-to-component spacing looks very close. It is workable, but could be a bit wider.

The pin of the gate resistor which is closest to the edge of the board seems a bit close to the body of the mosfet, under the board. You can create a pcb symbol for the mosfet which includes the silkscreen for horizontal outline. This also helps when you run the design check in the layout program.

The pins of the resistors which are closest to the bottom side of the VAS transistor seem too close to where a small heatsink would mount, if at the board level. Dual mosfets usually means higher supply voltage at the VAS transistor, so assuming the same bias current, more heat dissipation (I think about 30% more?). With the small-ish heatsink I am using, the temperature rise at the case of the VAS transistor on my board is around 20-25C at idle, and goes up from there.

Some of the elcos people are likely to use for the rail caps may have 1-mm pin size, so that means a bigger hole. This also applies to the diode which splits the rail at the VAS supply point, the diode would usually have a thicker lead diameter than the associated 10R.

Btw, the 10u film cap LC has used on his modules is 15-mm lead spacing.
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Old 5th July 2013, 03:49 PM   #839
shaan is offline shaan  India
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Quote:
Originally Posted by PMI View Post
@shaan: Some component-to-component spacing looks very close. It is workable, but could be a bit wider.

The FET's body isn't supposed to be in contact with the underside of the board; there will be no hole on the board for fixing the FETs. Both the N and P channel FETs will have their holes outside the board area, with say, 3-5mm gap between the them and the board. I did it this way coz otherwise the board length and width will have to be increased even more.

The pins of the resistors which are closest to the bottom side of the VAS transistor seem too close to where a small heatsink would mount, if at the board level. Dual mosfets usually means higher supply voltage at the VAS transistor, so assuming the same bias current, more heat dissipation (I think about 30% more?). With the small-ish heatsink I am using, the temperature rise at the case of the VAS transistor on my board is around 20-25C at idle, and goes up from there.

Some of the elcos people are likely to use for the rail caps may have 1-mm pin size, so that means a bigger hole. This also applies to the diode which splits the rail at the VAS supply point, the diode would usually have a thicker lead diameter than the associated 10R.

Btw, the 10u film cap LC has used on his modules is 15-mm lead spacing.
Thanks for the tips Pete. The spacing and hole diameter will be taken care of.

I am also thinking of splitting the circular ground trace near the input node, With two 10R resistors in series from upper trace to the lower, and then supply the input ground reference(0V in) and bias(10K) from the two resistor's junction. How does this sound? One can always short the resistors with jumpers if necessary.
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Old 5th July 2013, 04:24 PM   #840
PMI is offline PMI  United States
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Quote:
Originally Posted by shaan View Post
Thanks for the tips Pete. The spacing and hole diameter will be taken care of.

I am also thinking of splitting the circular ground trace near the input node, With two 10R resistors in series from upper trace to the lower, and then supply the input ground reference(0V in) and bias(10K) from the two resistor's junction. How does this sound? One can always short the resistors with jumpers if necessary.
For the input ground reference, I think that is a good idea.

I have to think about the bias ground.

In some other applications I am familiar with, a ground trace which circles the board can (although not necessarily will) cause some issues which then have to be overcome in other ways. What I am referring to is that as the load shifts from one rail to the other, an alternating current is generated in what is essentially a loop, and a loop antenna. The current reverses direction when the output signal crosses zero. So if you bring a small signal on a pair of wires close to that without additional shielding, there may be an issue. (note that I say "may", not will).

So splitting the ground trace in whatever way would help with that too, I think.
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