I think Mr Self has already written the book . . .
Wrong.
The list of topics to be included is now pretty much fixed, but I am still working on the text.
Well said, sir.
Just for the record, "unconditional stability" is a term borrowed from control theory, where it means that reducing the open-loop gain from a point where the loop is stable does not cause you to run into areas of instability as you continue to reduce it. Applying it to amplifier stability in the face of varying loads is a (very common) misuse.
The MJ802/4502 pair is, as you say, rather elderly. It does not sustain beta well. If you look at the beta plot on p165 of the 5th edition of APAD, MJ802/4502 would come somewhere between 2N3055 and MJ15024.
No.
Any topics added/amplified/tempered/deleted as a result of this thread ?
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I remember asking Mikeks ages ago whether DPC/TPC can be applied with a cascoded front end LTP. ie. to mitigate the negative rail reference/PSRR problem, so this can be sorted out.
It would be most interesting to see if TPC or dual pole (what bob cordell refers to as a T network) or whether the newer TMC can resolve this matter. If not we can safely put it in the bin.....
I suspect TMC is more likely to solve this.
We also need a vigorous test or series of test (standardised) to check c lipping and saturation behaviour. You also have settling and rise times.
Reactive loads and testing to the point of destruction. Do you have have a network analyser Douglas? Basically we need in-situ phase measurements if possible with different loads and clipping/saturation/rail sticking etc etc behaviours.
Bob Cordells 1982 or '84 design was purely theoretical and had no PCB layout, full schematic/components etc and as far as I am concerned you might as well put it in the bin. Complete waste of space. There is absolutely no evidence nor measurements it could slew at 300V/us or have THD20K @ 0.001.
Do people think about the PCB design involved to get 120db of dynamic range, sub 0.001% @ 20Khz, induction problems from the rails, capacitor leakage, earth returns, NFB take off points, optimum RC snubber networks for the rectifiers, and so on. Then add discrete components which become increasingly ineffective after 1 Mhz ?
There is 500 ways with PCB design alone to screw it all up.
As Douglas Self himself said in a riposte to JLH in his remark, that he does not believe THD measurements below 0.001% had any credibility in his experience, was that the only reliable way of testing sub 0.001 THD distortion is with a A.P. system 1 (itself involving 50+ patents I believe!). I think the AP system 1 was mid 90's equipment....not '82 or '84....
Hope you deal with series regulators or some some of triac design (dc overload protection). Remember FETs and BJTs short - Dual/triple slope VI is a complete waste of space in my opinion. Anything involving fuses also.
Wish you well. And hope the book really good.
Best Regards
Kevin
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Maybe its been said already, maybe its of no interest, maybe its already included and I didn't see it.
But I've seen more requests for grounding schemes on this forum, than any other question.
Newcomers ask about how to wire especially ground wiring, mono amp, stereo amp, with and without preamp.
How to layout simple bridge capacitor power supply board and how to avoid ground loops,
Its my opinion that clear graphic representation works better than explaining in text alone.
Regards
But I've seen more requests for grounding schemes on this forum, than any other question.
Newcomers ask about how to wire especially ground wiring, mono amp, stereo amp, with and without preamp.
How to layout simple bridge capacitor power supply board and how to avoid ground loops,
Its my opinion that clear graphic representation works better than explaining in text alone.
Regards
>Bob Cordells 1982 or '84 design was purely theoretical.
Kevin,
Are you talking about his error correction amp?
Hello Edmond,
Yes I was. Actually I was tired and not feeling very well when I wrote it. Some of it was hastily written. The point I was making of course, is the importance of PCB layout to all this. I am no way trying to put down Bob Cordell - he's an awesome amp designer and seems a nice guy as well.
The only amp I have seen slew at over 300V/us (and measured) on both sides is the stochino amp written in EW&WW. That had I think a dual differental Class AB input and quite a fancy compensation scheme.
Actually thinking about there is probably lots of ways in op amps to get THD20K under 0.001% but they can use multiple loops etc. I think someone said he knew one with five loops in it!
I will get back to you later Edmond as I know your good with a simulator with something(s) to check with DPC and TMC and it's all to do with negative PSRR.
I have got go out somewhere, be back later
Best Regards
Kevin
TMC provides 2-pole loop gain around the output stage, looks “single pole” back to the input of the VAS/TIS
this means the "extra" loop gain is not available to improve the LTP characteristics, nor the VAS/TIS supply reference PSRR – except through a slight change in the available global outer loop single pole gain from the TMC bootstrapping increasing VAS/TIS loop gain
PSRR is dominated by the VAS/TIS and compensation reference being a power supply rail - normally the PSRR of that rail will look like the loop gain, measured around the VAS/TIS
I believe Doug has shown one of the schemes to reference the compensation to gnd instead of a rail
classic 2-pole, TPC added loop gain can improve everything measured by the LTP within the the global feedback - all the LTP errors that the feedback/differencing operation can measure
neither can do anything about common mode V induced errors of the input stage - input cascode are good for any compensation scheme
its just that these CM input errors are usually so small they can't be seen until you have reduced the other bigger distortions of the rest of the amp
some discussion (starts above), my post gives a reference: http://www.diyaudio.com/forums/soli...lls-power-amplifier-book-217.html#post2695213
“A General Relationship Between Amplifier Parameters, And Its Application to PSRR Improvement” E Sackinger, J Groette, W Guggenbuhl, IEEE Trans CAS vol 38, #10 10/83 pp 1171-1181
is really the ref Doug should add to his book
this means the "extra" loop gain is not available to improve the LTP characteristics, nor the VAS/TIS supply reference PSRR – except through a slight change in the available global outer loop single pole gain from the TMC bootstrapping increasing VAS/TIS loop gain
PSRR is dominated by the VAS/TIS and compensation reference being a power supply rail - normally the PSRR of that rail will look like the loop gain, measured around the VAS/TIS
I believe Doug has shown one of the schemes to reference the compensation to gnd instead of a rail
classic 2-pole, TPC added loop gain can improve everything measured by the LTP within the the global feedback - all the LTP errors that the feedback/differencing operation can measure
neither can do anything about common mode V induced errors of the input stage - input cascode are good for any compensation scheme
its just that these CM input errors are usually so small they can't be seen until you have reduced the other bigger distortions of the rest of the amp
some discussion (starts above), my post gives a reference: http://www.diyaudio.com/forums/soli...lls-power-amplifier-book-217.html#post2695213
“A General Relationship Between Amplifier Parameters, And Its Application to PSRR Improvement” E Sackinger, J Groette, W Guggenbuhl, IEEE Trans CAS vol 38, #10 10/83 pp 1171-1181
is really the ref Doug should add to his book
Hello Jcx, or John,
Fantastic post.
You quote:-
"I believe Doug has shown one of the schemes to reference the compensation to gnd instead of a rail."
Do you know any/the other ones?
I am certain there is other ways of doing it. I think it was Sy that mentioned another one, and Self already knew this, but that was ages ago on diyaudio.
See I am already discouraged with TMC, in that it includes a Class B commutating stage in the loop at even higher frequencies than a normal miller cap, with its incipient problems of switching and supply rail modulation. And I suspect will exacerbate negative rail PSRR problems.
So DPC seems to be the winner so far, but the people I have spoke to looking at DPC in compensation matters would not touch it with a barge pole! I do not know what the problem is with it personally.... I know some of these guys know much more about compensation matters than I do.
Mikeks once offered me his paper on compensation for £1500. About $2280 at todays exchange rate. I was like screw that!. I do not even make amps for a living!
Will add more later on
Best Regards
Kevin
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Till now, I thought I was the only one who received this generous offer.
You don't know what you're missing.
There is no such thing as MIC ("Miller Input compensation"). As I pointed out somewhere, it is really phase lead compensation with the output stage excluded; certainly, pole splitting does not occur with this arrangement, which explains why other supplimentary compensation is invariably required.
Simple SPICE simulation demonstrates these facts, so both D. Self and R. Cordell were wrong in calling it "input stage inclusive compensation". Moreover, it has nothing to do with Mr J. M. Miller, so it should never have been called "MIC".
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