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Old 10th February 2013, 06:46 AM   #11
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Originally Posted by keantoken View Post
Cascoding would make Hfe more stable.
Are you referring to adding a cascode stage to handle the voltage swing and keep Q2,8 at low voltage?
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Old 10th February 2013, 06:51 AM   #12
jcx is online now jcx  United States
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Besides, I can always remove the mirrors and replace them with fixed resistors and set the VAS bias that way, but it will give away a few dB of gain.
you'd best do that now - before wasting more sim cycles

and wasting other poster's time time trying help when the basic circuit topology doesn't work reliably
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Old 10th February 2013, 07:08 AM   #13
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Originally Posted by jcx View Post
you'd best do that now - before wasting more sim cycles

and wasting other poster's time time trying help when the basic circuit topology doesn't work reliably
How about contributing to the question at hand instead?

What can we gain from looking at the Bode Plots on loop stability?

I'll work on the actual circuit soon enough and find out what will and will not actually work with real parts on a real circuit card. The whole point of my post was not to critique the design, but to understand the Bode Plots and their relationship to loop stability.
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Old 10th February 2013, 07:31 AM   #14
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There are some compensation configurations that make the loopgain plots confusing. For instance I had an amp that caused phase to wrap around the plot. I'm not exactly sure what's wrong in your case but since I can't tell from the schematic how you're deriving loop gain, I suggest you might be doing it wrong like djoffe says. Look in the /example/loopgain2.asc file in the LTSpice directory and use that method.
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Old 10th February 2013, 07:52 AM   #15
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OK, I updated the schematic and removed the mirrors and added the cascode stage for VAS. The cascode is biased by a current source to maybe 3V from the rail. I ran new simulations on open and closed loop and got the Bode plots. Same questions still.

What on the plots reveals loop stability/instability?

BTW, the cascode stage using the 2N5551 and 2N5401 for gain and the MJE340 and MJE350 for the swing voltage added more than enough gain for what was lost by removing the mirrors. VAS bias current is set to 20mA with this setup.
Attached Images
File Type: gif Open loop gain with cascode.gif (17.0 KB, 104 views)
File Type: gif closed loop gain with cascode.gif (17.2 KB, 101 views)
File Type: gif 10 tone FFT Hann- 60V peak - 8 Ohm cascode.gif (20.5 KB, 101 views)
File Type: gif Cascode Gain Stage.gif (33.2 KB, 85 views)
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Old 10th February 2013, 07:54 AM   #16
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Originally Posted by keantoken View Post
There are some compensation configurations that make the loopgain plots confusing. For instance I had an amp that caused phase to wrap around the plot. I'm not exactly sure what's wrong in your case but since I can't tell from the schematic how you're deriving loop gain, I suggest you might be doing it wrong like djoffe says. Look in the /example/loopgain2.asc file in the LTSpice directory and use that method.
To generate loop gain, I put a 1F capacitor at the (-) input to ground to basically short it out without removing the DC portion.

I'll check out their suggested method and see if it does anything different.
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Old 10th February 2013, 07:56 AM   #17
jcx is online now jcx  United States
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post the .asc? - now an allowed forum file attachment type - I put any non-standard Q .model defs directly on the schematic for portability
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Old 10th February 2013, 08:07 AM   #18
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The circuit looks unrealistic to me. You really expect to use a 1pF compensation capacitor? That is probably less than circuit stray capacitance. 301k for the feedback resistor? This is 10 times more than usual. No LTP emitter resistors? The theoretical extra loop return ratio is impractical I think.

David Zan
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Old 10th February 2013, 08:08 AM   #19
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Originally Posted by jcx View Post
post the .asc? - now an allowed forum file attachment type - I put any non-standard Q .model defs directly on the schematic for portability
I'm using Cordell's models for all the devices in the schematic.

I also derived the open loop gain by simply dividing the output by the difference between the (+) and (-) inputs at the JFET gates. I get the same thing by shorting the (-) input with a 1F capacitor. The open loop gain plot I posted is no different than the actual method for determining open loop gain, Vout/(V(+) - V(-)).
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File Type: asc Nested Differential cascode.asc (21.2 KB, 16 views)
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Old 10th February 2013, 08:23 AM   #20
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Originally Posted by Dave Zan View Post
The circuit looks unrealistic to me. You really expect to use a 1pF compensation capacitor? That is probably less than circuit stray capacitance. 301k for the feedback resistor? This is 10 times more than usual. No LTP emitter resistors? The theoretical extra loop return ratio is impractical I think.

David Zan
Hi David,

As for LTP resistors, I've put them in, and taken them out. 100 Ohm was the value I originally tried, and with this particular circuit, they didn't seem to make much difference one way or the other, either in open loop gain or closed loop gain or performance in general. Cleaner schematic without them.

As for compensation capacitance, who knows what it will actually be once the circuit is laid out and soldered up. For simulations, that's what worked.

301K feedback resistor with a JFet device is quite reasonable. If I do reduce it to 30.1K and the 10K to 1K, then the 1pF compensation moves to 10pF to keep everything on the bode plots the same and producing stable output.
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