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Old 15th December 2012, 08:12 PM   #1
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Default bjt jfet CFP diff input stage

I im designing a new amplifier and found this interesting article:

Memory Distortion Philosophies - Part 4 : Circuits

As from the link i would like to simulate this input stage in LTSPice...and if anyone could help me how to simulate for now only input stage(Linearity, Gain, SlewRate, THD, etc...)

here is example input stage only with bjt:

https://sites.google.com/site/fabaud...ge_low_mem.jpg

As you can i add p-jfet and n-jfet to bjt. Together i get all the benefits from bjt and jfet so linearity need to be perfect.

For jfet i have choose 2SK170/2sj74 from Toshiba
For bjt i have choose 2SA970/2SC2240 from Toshiba

Between Resistors R3/R4 it must go to CCS Source, and from J1/J2 Drain it gets to Current Mirror With Two Bjt Transistors (2SA970/2SC2240).

What do you guys suggest to be the best CCS Source and Current Mirror or should i use other suggetions?

I im attaching LTSpice file with schematic if someone could add commands to simulate only this input stage and uplodad it here so we can discuss here what is better and to fine tune this input stage (High Linearity, Slew Rate...)

Many Thanks.

And if someone can add models Toshiba 2SA970/2SC2240 and JFETs (2SK170/2SJ74 Toshiba).

Click the image to open in full size.
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Old 15th December 2012, 08:54 PM   #2
Bigun is offline Bigun  Canada
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There is a serious problem with the memory distortion for me, which makes it difficult to consider the extra complexity. The premise and the theory is good. But the CFP and the casdoding both significantly improve the performance of the circuit even if there is no memory effect at all. So when comparing the simple single device with complex circuit you can't separate out what improvement is from elimination of the memory effect and what is simply a much more linear circuit. So for me, there is no evidence that improvements are due to reduction of memory effect.
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Old 15th December 2012, 08:57 PM   #3
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Ok...so can you recommended me what is your choice for input stage that is high end (High Linearity, Gain, Low THD....)

If you can post schematic or link with theory for input stage.
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Old 16th December 2012, 01:28 AM   #4
Bigun is offline Bigun  Canada
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Hey I wasn't saying that the design you are looking at is bad, in fact it looks to be pretty high end to me with good linearity. I'm just saying that I didn't see evidence that memory distortion is an issue. I think the input stage you posted can stand on it's own feet without reference to memory distortion, it is a very worthy design.

Are there better input stages ? - I'm not sure, but there are several on the forum that also look good. I can't say if one is best.
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Old 16th December 2012, 07:05 AM   #5
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Generally speaking, BJT's are great for driving the source of a common gate J-fet amplifier. Driving the source with a dependent current source (collector) mitigates the non-linear changes in Vgs vs Id. In fact the VAS of the stereo module I made is complementary common gate J-fet. But, I recomend that the next stage be buffered or have a high (AC) current gain.
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Old 16th December 2012, 08:09 AM   #6
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Thanks...i will study this input stage...could some help me with LTSpice simulation? I would like to simulate only this input stage without VAS, Buffer and Output stage.
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Old 16th December 2012, 10:57 AM   #7
forr is offline forr  France
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Robydream

I would like to simulate only this input stage without VAS, Buffer and Output stage.

Memory distorsion is certainly an interesting concept. But nobody (my self included, I made numerous tests) has yet proved it to occur in standard negative feedback amplifiers.
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Old 16th December 2012, 11:01 AM   #8
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Hi robydream

One quarter (combined transistor) of your circuit should be like this. Well tested in practice.
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Old 16th December 2012, 11:03 AM   #9
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Hi Lazy Cat... i see, do you have any schematic that have this input? I see that Dr. Bora have use this topology for input stage in his design epsilon

http://bas.elitesecurity.org/epsilon-schematic.pdf

Any schematic more?
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Old 16th December 2012, 11:10 AM   #10
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It is not the same, gate of a fet should be connected to emitter of the input BJT, this way you have even more constant conditions for input BJT.
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