Alternative buffer topologies

[Elvee]

Originally Posted by kf_tam

1.Simpler circuit, no need for the four bias diodes (Q5/6/12/13)
2.More options of dual transistors of same sexes than mixed sexes (THAT?)
Disadv:
3.Slew rate is limited by current source at LTP's tail.

I don't think a marginally reduced BOM is really an advantage, and in this circuit only the same polarity pairs need to be matched: P and N devices need not be exact complements (OK, they cannot be totally different but that is not quite the same).
I think the loss of SR is not a minor issue

But if Q8~11 are replaced with complementary JFET pairs, then it is a whole new ball game.
4.If connected as Rush cascodes there are no need of Q5/6/12/13 and I3/5 due to the self biasing nature of JFET.
5.If connected as two LTPs (as John Curl/Sansui diamond differentials), you don't need current sources at LTP tails so slew rate is faster.
6.Disadv: complementary JFETs have few options, low voltage and power rating.

It is tempting, but:
The Vgs matching between N and P devices will be poor, and this means the offset issue will come back.
And with dual complementary FETs, it is not an easy cheapo circuit anymore.
But thanks for your ideas anyway, I am sure they will appeal to some.

[lineup]

I have setup a circuit using 2SK170+2SJ74 for the feedback loop.
I have a small trimpot on the input to adjust DC Offset.
As you say it is very different VGS for the NJFET and the PJFET.

But anyway with IRFP240 + IRFP9240 output the circuit is promising.
It will NOT be as precise as with bipolar transistors
but it will be quite a bit simpler circuit.

[MiiB]

I like the first simple circuit....but could it not be made with laterals where you take the signal from the Drains...??
I belive the DC issue could be solved rather simple, by adding a servo that alters the current in on the second pair of current sources

[lineup]

Originally Posted by MiiB

I like the first simple circuit....but could it not be made with laterals where you take the signal from the Drains...??
I belive the DC issue could be solved rather simple, by adding a servo that alters the current in on the second pair of current sources

I did a version for testing Laterals.
Unffortunately the low VGS made it impossible to fit the diamond inside the loop.
If one wants to use Laterals there should be another solution, like adding BJT drivers to the Gates.

[MiiB]

here you have a compound..

I too tried to make your buffer work with laterals, but had no succes, thats why I ask for this solution where you take signal out on the drains.

[Elvee]

Here is a jFET variant, along with a trick avoiding intersex matching and therefore big offset issues.
The THD is three times worse than the bipolar front-end, but it remains acceptable

[Elvee]

.... And for the sake of completeness, a MOS version.

Not very good: the THD has suffered a twenty fold increase

[kf_tam]

Originally Posted by Elvee

Here is a jFET variant, along with a trick avoiding intersex matching and therefore big offset issues.
The THD is three times worse than the bipolar front-end, but it remains acceptable

Thanks for the effect, but if I am not mistaken the JFETs are all connected as source followers

Here is a Japanese link that shows a JFET Rush cascode front-end driving Toshiba MOSFET. The designer has put in two LEDs to give more voltage headroom to the front-end. One end of the current source is adjustable to take care of the offset. He also "cheated" somewhat with the bias regulator to give some negative feedback. All in all, a designer with many different ideas.

Best Regards,
Edward Tam

[kenpeter]

All I was sayin'...

[Elvee]

Originally Posted by kf_tam

Thanks for the effect, but if I am not mistaken the JFETs are all connected as source followers

In an environment where all nodes move synchronously to within mV of each other, defining a "common" terminal is an interesting exercise in relativity.
Basically, devices present a transconductance between two ports and two other ports, of which one is common.
But this commonality is completely local, and you are free to define any node as globally common

Here is a Japanese link that shows a JFET Rush cascode front-end driving Toshiba MOSFET. The designer has put in two LEDs to give more voltage headroom to the front-end. One end of the current source is adjustable to take care of the offset. He also "cheated" somewhat with the bias regulator to give some negative feedback. All in all, a designer with many different ideas.

A good example of what I wanted to avoid.

What do you think will result if P and N devices do not have exactly the same Vgs at the bias current, and more subtly, what will happen if this Vgs does not track with temperature?
Another interesting question is the overall transconductance of the input compound.

And all of this assumes the jFETS are capable of taking the full voltage swing of the supplies and the resulting dissipation.

The result is shown:
Even with the perfect complements 2SJ74/2SK170 of the sim, a 6.5mV offset appears (in reality, it would be much worse), and the THD is increased by almost a hundred fold.