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I wrote: gm ~=Ic/26mV and notice the tilde. Whether this equation is correct doesn't matter, as I didn't use it for any calculation at all.

~ doesn't mean on my side of the channel over +/-100%. The equation wouldn't matter if everything would be linear, which is not.

Otherwise, just stay in your simulation world. It may look like you are always right (in particular when not being specific on all the details, like schematics, models, methods, etc...), and also reading on a topic (I already suggested some good references) is not required.

I think it's time to update again your **** list.
 
The usual confusion between a small signal, linearized, and a large signal analysis. gm=Ic/26mV holds for small signal only.
Yes, it is directly derived from the exponential junction equation, it is the slope of the curve at that particular Ic. It is therefore valid only for infinitesimal variations around that point.
But more generally, if a gm remains constant for a range of currents, this implies that the element is linear for that range

There is no simple way to calculate the large signal transconductance. The large signal analysis of an emitter follower with Re does not have any known analytical closed solution.
It makes no real sense for a highly non-linear element

I wrote: gm ~=Ic/26mV and notice the tilde.
Whether this equation is correct doesn't matter, as I didn't use it for any calculation at all. My simulator did the calculations, which also takes care of large signal and other effects. And please don't start whining again about the accuracy of simulators. For the purpose at hand they are accurate enough.

The point is that the composite gm of the bipolar output trannies plus emitter resistors did not reveal the gm doubling at large currents. That means you can't use it for explaining the distortion. Perhaps you forgot it, but we are talking about the real cause of distortion: is it bias voltage modulation or is it gm modulation. According to my last plot (black curve) it is not gm modulation.
The devil is in the details, in this case the practical ones: the various parameters used for the simulations.
For an ideal transistor pair having no Re, internal or external, a non-linearity will already be present: for the pair to remain linear, the sum of the collector currents would need to remain constant, but that is never the case, even in the "class A region". With a constant base bias, instead of a constant sum of Ic's, we have a constant sum of the logarithm of the currents.
For small excursions around the quiescent state, this is more or less equivalent, but as soon as one current becomes large, discrepancies occur.
Let us take a numerical example: if the bias voltage is such that it establishes an Iq of 100mA, an output current causing a shift (bias modulation if you like) of 20mV will ~double the current in one of the transistor, resulting in Ic=200mA, and it will halve the current in the other one, but that is not enough: to keep the sum constant, it would need to be 0. We therefore have a 50mA excess, and a corresponding increase in the transconductance.
In this case, the gm is minimal at the equilibrium, and increases proportionally to the excursion.

If emitter resistors are added, this effect can be mitigated and even reversed, but they will not make the OPS linear: with devices obeying an exponential law, that is an impossibility. Only square law devices could achieve that

Otherwise, just stay in your simulation world. It may look like you are always right (in particular when not being specific on all the details, like schematics, models, methods, etc...), and also reading on a topic (I already suggested some good references) is not required.
That is precisely because the sim is accurate enough that "unexpected" effects show
 
Elvee, I know this already, but it's beside my point. Moreover, my simulator takes care of all these matters.
I'm talking about the difference between the 'green' and the 'black' incremental gm (see post #118).

The first one is simply gm = delta Io / delta ( Vi - Vo ), where Vi = ( Vb1 + Vb2 )/2 and Vb1 and Vb2 are the base voltages of the top respectively bottom output tranny. Notice that ( Vb1 + Vb2 )/2 = Vb2 + Vbias/2 = Vb1 - Vbias/2. IOW, the bias voltage has been taken into account.

While the second one consists two gm's (of top resp. bottom tranny) summed together:
gm = delta Ie1 / ( delta( Vb1 - Vo ) + delta Ie2 / delta( Vo - Vb1 ) ), were Ie1 and Ie1 are the emitter currents of top respectively bottom output tranny
In this case the bias voltage has not been taken into account.

Not surprisingly, we get two different gm figures. Now, which of the two is correct, the green one or the black one?

Cheers,
E.

PS1: Vb1 and Vb1 are base voltages WRT ground, thus not Vbe.
PS2: Walter, you are not supposed to comment on this post.
PS3: I corrected the equation for the black gm.
 
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Okay, here it is:
 

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Okay, here it is:
I don't get the same anomaly: the two curves are perfectly overlaid.

I see two possibilities: your V(A) varies with respect to V(B): the two expressions are equivalent provided dV(A,B)=0

Another possibility is an ambiguity in the sign convention in the simulator resulting in quantities subtracting instead of adding under certain conditions.
 

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I don't get the same anomaly: the two curves are perfectly overlaid.

I see two possibilities: your V(A) varies with respect to V(B): the two expressions are equivalent provided dV(A,B)=0

Another possibility is an ambiguity in the sign convention in the simulator resulting in quantities subtracting instead of adding under certain conditions.

Hi Elvee,

Of course the two curves are just the same, simply because this is an ordinary class-AB OPS without sliding bias.
If you are in the mood, you could repeat the sim with sliding bias. To keep it simple, just replace V4, by a CCVS that keeps I(R8)*I(R9) constant. For an idle bias of 100mA for example, set the product at 0.01.
Of course such circuit is not exactly the same as a PA0016, though it comes close as far as bias concerns.
Here's an example with mosfets and a CCCS that keeps product of source currents constant: CDCP

Cheers,
E.
 
Hi Elvee,

Of course the two curves are just the same, simply because this is an ordinary class-AB OPS without sliding bias.

Then I think your results are perfectly normal: you sort of expect f(x+y) to be equal to f(x)+f(y), which is not generally true if f is a non-linear function.

To measure independently the transconductances of each half under those conditions, you could add another stimulus source, independent of the excitation(s) (signal and sliding bias), and use it to measure the resistances or output conductances of each half, or both together.
By plotting these values against the excitation, you would get a consistent picture.
You could place a current or voltage source in the output for example.
 
If that was the reason, then we shouldn't get equal result with a fixed bias, because also in this case we have to do with two nonlinear functions.
No, because they don't interact with each other, and because the quantities analyzed are not identical: the dV(C,out) includes half of the sliding bias which is correlated to the signal, which dV(A or C, out) doesn't.
 
Here is more or less what I suggest to disentangle unwanted correlations.

It is very clumsily made, and the output format is highly inconvenient, but I am sure someone more versed than I am in spice could do it in an elegant manner and produce a nice and clean graph. This is just to show the principle.

Basically, the original stimulus is swept through a range of values (with a sliding bias, V4 has to follow), and the output conductance is measured using a different source, in this case AC analysis because I found it the simplest method.
You can plot the global transconductance and that of each half, I am sure you will find consistent results (ie global transconductance= sum of each half)
 

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Center point C

No, because they don't interact with each other, and because the quantities analyzed are not identical: the dV(C,out) includes half of the sliding bias which is correlated to the signal, which dV(A or C, out) doesn't.

Hi Elvee,

First, a Happy New Year,

>the sliding bias which is correlated to the signal
That's what it's all about. In post #118 I asked: tell me what I did wrong? Of course I really did already know what was wrong about it. But I felt it important that someone else figured it out. And why was that? Because a few DIYers think that gm modulation is the principle cause of distortion. Well, it's not, instead, it is the variable bias voltage that causes the distortion, which becomes clear if you take point A, B or C as input. Gm variation is just a 'synthetic byproduct' derived from bias variation. Admittedly, it also correlates with the amount of distortion, but it isn't the real cause. And why is that so important? Not just because it doesn't harm to know what's really going on, but also you must made a decision which point (A, B, C) should be used as (effective) input, or in the example below, which connection should be chosen as take off point for the Miller compensation. The schematic is from Bob Cordell's 'Designing Audio Power Amplifiers' page 547 and he did it in the right way: point C in order to minimize the effect of nonlinear bias modulation.

Cheers,
E.
 

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DiAna

Merry Xmas Edmond!
How is your distortion analyzer coming on my the way?

/OT
Hi Andrew,

Firstly, A Happy New Year.
As for the distortion analyzer, thanks to a (rather obscure) article I found on the web: http://evergreen.loyola.edu/mpknapp/www/papers/knapp-sv.pdf I made some progress.
With the help of this article I can exactly compute things like amplitude, offset, phase and frequency. But more importantly, this article enables me to find the solutions in an analytic way, thus not via a tedious trial-and-error approach.

Cheers,
E.
 
Hi Elvee,

First, a Happy New Year,
Thanks Edmond, the same to you.

That's what it's all about. In post #118 I asked: tell me what I did wrong? Of course I really did already know what was wrong about it. But I felt it important that someone else figured it out. And why was that? Because a few DIYers think that gm modulation is the principle cause of distortion. Well, it's not, instead, it is the variable bias voltage that causes the distortion, which becomes clear if you take point A, B or C as input. Gm variation is just a 'synthetic byproduct' derived from bias variation.
I think we have to be extremely careful, and things could well be even more subtle than that.
We have to distinguish "real effects" from artifacts caused by the way we use the simulators. When you hack the OPS in two parts, analyze them separately then add the two results as a sanity check, and see anomalies appear, it doesn't mean the anomalies are real, simply that you performed some illegal operation in this context.

Admittedly, it also correlates with the amount of distortion, but it isn't the real cause. And why is that so important? Not just because it doesn't harm to know what's really going on, but also you must made a decision which point (A, B, C) should be used as (effective) input, or in the example below, which connection should be chosen as take off point for the Miller compensation. The schematic is from Bob Cordell's 'Designing Audio Power Amplifiers' page 547 and he did it in the right way: point C in order to minimize the effect of nonlinear bias modulation.
I think point C is misplaced in this schematic.
Anyway, we have to deal with three separate effects: the artifacts caused by an improper use of simulation, the first order injection of the sliding bias into the "noble path", and the parametric effect of the sliding bias on the signal path.
We have more or less dealt with the first point.

The second point is what I call an imperfect orthogonality between the noble and control paths.
In the example of the simple OPS, this effect can be minimized by making the sliding bias symmetrical about the drive voltage (what should be C), and making the OPS as symmetrical as possible.
This should eliminate most of the "leaks" of the control into the noble signal.

And then we have the modulation effects: with the sliding bias algorithm you have used, its effect is to render the OPS "perfect", simulating an ideal pair of transistors without emitter resistors, internal or external (but without the risks associated with such a configuration).
However, this predictably increases distortion compared to an optimal combination of emitter resistors and bias current, because of the purely exponential characteristic.
When a suitable resistor is added, it provides a break-point grossly approximating a square law characteristic.
To actually reduce distortion compared to this practical optimum, one would need to generate a law more complex than In*Ip=constant
 
We have to distinguish "real effects" from artifacts caused by the way we use the simulators. When you hack the OPS in two parts, analyze them separately then add the two results as a sanity check, and see anomalies appear, it doesn't mean the anomalies are real, simply that you performed some illegal operation in this context.

BINGO! I couldn't put it better.
 
pointless point

I should probably clarify what I mean: node C is suitable for analyzing the behavior of the output compact (and application of the compensation), but it is not on the same level as A and and B, and cannot be used for comparison purposes (not directly anyway).

If A or B were on the same level, a comparison would be pointless.
So, what's your point?
 
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