Biasing output stage FETs

Status
This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.
Hi Guys,
Can anyone point me to an online tutorial, or give me a breif overview of how to bias output stage fets for a class AB amp?
This is my first attempt at a fet amp, and although I could just copy an output stage from someone else's schematic, I'd like to get an understanding of what's going on...I don't want to blow up those expensive devices!!! (2sk1058 & 2sk162)
I'm planning on driving them with an SRPP valve stage, via a capacitor, not direct coupled, and using a single ended power supply taking the speaker out via a cap., (this amp will be for guitar, you audiophiles can relax...)
so the biasing arrangement should be fairly simple, I'm just not sure how to work the numbers.

any help for this newbie would be appreciated,
cheers, Pete McK
 
It would be much easier to help if you post a schematic of what you have so far. I have no idea how you are configuring the OPS.

PeteMcK said:
Hi Guys,
Can anyone point me to an online tutorial, or give me a breif overview of how to bias output stage fets for a class AB amp?
This is my first attempt at a fet amp, and although I could just copy an output stage from someone else's schematic, I'd like to get an understanding of what's going on...I don't want to blow up those expensive devices!!! (2sk1058 & 2sk162)
I'm planning on driving them with an SRPP valve stage, via a capacitor, not direct coupled, and using a single ended power supply taking the speaker out via a cap., (this amp will be for guitar, you audiophiles can relax...)
so the biasing arrangement should be fairly simple, I'm just not sure how to work the numbers.

any help for this newbie would be appreciated,
cheers, Pete McK
 
that's it!

Hi DShort,

Thanks for the links
The second link you provided is pretty much the amp i'm building, just with lower voltages; 40v for the FEts and 80v for the valve, which will be a 12ax7.
I suppose I'm just trying to get an understanding of what the proper gate to source voltages should be.

Cheers, Pete McK
 
Biasing Fets

Doing the math shows the mosfets in the schematic being biased at 1.27 volts each. This should give about 500ma of idle current according to the data sheet.
I am concerned with using a 12AX7 as you will only have a couple of ma. of current to drive the mosfets.
The math can be found at this link http://www.tubecad.com/november99/page3.html
This shows that you need a minimum slew rate of 5v/us. and 7.5 ma. to accomplish this at 20khz, using the combined capacitance of the mosfets. Keep in mind that this will give you a waveform resembling a triangle at 20khz, and phase beginning to fall off at 2khz.
 
Status
This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.