A distortion-cancelling buffer

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JFET Q1 operating with only 0.65VDS = Q3VBE?
The gate will almost have to be in forward bias...

This scheme makes sense when Q1 was a BJT.
Someone tried too hard to improve, and broke it.

Q1's input impedance can't be much more than
Rs in series with its own forward biased gate.

What point is low distortion and JFET if the input
Z are low and non-linear? You have to drive with
near zero impedance to get low distort out... And
if you have that, why you need a follower?
 
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What I found interesting was the use of a jFET input. This is advantageous with this type of circuit, because of the negative input impedance issues, which can be problematic when the input device has a sizeable input current.
The circuit may have some weaknesses, but they could probably be addressed without too much difficulty.
 
The Vds could easily be increased by adding one or two forward biased diodes in series with the emitter of Q3 (and adapting the correction accordingly).
Q3 could also be replaced by a complementary P-jFET

Louis, you can do the same cancellation in Tringlotron 🙂
I used MOS in the tringlotron because FETs were a bit weak to drive headphones directly, but the goal is the same.
 
JFET Q1 operating with only 0.65VDS = Q3VBE?
The gate will almost have to be in forward bias...

Even if a suitable JFET was found with negative gate bias in those conditions -> read, high gm

The saturation condition (where the small signal jfet model holds, don't confuse with the bipolar saturation) for a jfet is Vds>Vgs-Vp where all terms are to be considered algebrically. The closer the bias current to Idss, the larger Vds is required.

Examples:

- for a N channel 2SK170, Vp~-0.6V and Vgs for a typical bias point is ~-0.2V Therefore Vds > -0.2+0.6=0.4V. If the device is biased close to Idss (Vgs=0) then Vds needs to be > 0.6V. In both cases Vds=0.6V as in the schematic is ok.

- However, for a J202 with the datasheet Vp=-0.8...-4V, if you bias such a device close to the datasheet Idss (0.9...4.5mA, for Vgs=0V), then Vds > 0.8...4V and the proposed bias point of Vds=0.6V is not good. The solution is to bias the J202 well under Idss, to make the saturation condition valid at Vds=0.6V (but then the stage transconductance will be lower).

Biasing at very low Vds requires very close analysis of the datasheet for the worst case of device parameters combination. It can always be done (whatever Vp, there is always a Vgs that ensures saturation at Vds=0.6V), but not without some tradeoffs (lower stage transconductance, when Vgs approaches Vp and hence Id decreases significantly).
 
Here is the circuit modified to increase the FET's Vds with two diodes.

A fascinating by-product of the positive feedback is not only the reduced distortion, but also the fact that this buffer exhibits a gain greater than 1!!!
Unfortunately, it is quite sensitive to the output loading.

In this respect, UniGabuf remains far superior, but at the cost of a significantly larger complexity
 

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