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Old 19th November 2012, 10:55 AM   #21
AndrewT is offline AndrewT  Scotland
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Originally Posted by CBS240 View Post
Consider placing a zero ~30MHz (Zobel filter) from gate to drain ............... and you will be able to reduce the gate stopper. This will increase the Fc of the LP filter created by the gate stopper and the input capacitance while still being able to critically dampen the oscillator created by the mosfet internal components..........
Could you post a schematic?
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Old 19th November 2012, 11:17 AM   #22
lineup is offline lineup  Sweden
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Well, it is one of those things that you have to abandon the simulator for. Simulator amps don't make much sound. The parasitics of the PCB/wiring is not so easy to model in a simulator.
I wish we could add such things into simulator.
As wire resistance and inductance.
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Old 19th November 2012, 05:17 PM   #23
Bonsai is offline Bonsai  Taiwan
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You can model the parasitics. The inductances around the output and drive stages are particularly important, but 5-10nH per cm or thereabouts will soon let you know if you have a problem. Here's a link to a cascode related problem where the board pcb traces were modelled

http://hifisonix.com/wordpress/wp-co...mplifiers1.pdf
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Old 19th November 2012, 07:41 PM   #24
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http://www.ti.com/lit/an/snaa045/snaa045.pdf
Paragraph 7.1 page 17
"Dertermining gate resistor values"
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Old 19th November 2012, 08:22 PM   #25
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If you drove a signal straight into the capacitance of the gate it would overload the driver stage and cause instability.
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Old 20th November 2012, 01:48 AM   #26
CBS240 is offline CBS240  United States
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Quote:
Originally Posted by AndrewT View Post
Could you post a schematic?
Refer to page 7 of Bob's Mosfet paper. It is a good illustration.
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Old 20th November 2012, 06:45 AM   #27
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Well, it is one of those things that you have to abandon the simulator for. Simulator amps don't make much sound. The parasitics of the PCB/wiring is not so easy to model in a simulator.
I'm not sure if I understand you correctly, but I was agreeing with you I use the same technique in my currently playing MF80 amp. You're right that the sim doesn't show the oscillations, the parasitic L's are not modeled in the MOSFET models I was using. But on the bench, with my 200MHz scope I could make visible a 85MHz oscillation. In practice, a 47pF cap from drain to gate per FET was enough to have them shut up. N gate stoppers are 18 Ohm, P gate stoppers 15 Ohm. The stage is bloody fast.
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Old 20th November 2012, 06:50 AM   #28
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AndrewT, you have to look at it like this and in a sudden you'll get it being very easy:

Think of the power FET as an opamp with a non-inverting input (Gate) and an inverting output (Drain). Witih opamp circuits you often put a 10pF from the output to the antiphase input. This is similar in where you connect the transistor inverting output back to its input with a HF bypass. With this, forget that drains are connected to powerlines; it doesn't change the conceptual view of the drain being an inverting output to the gate.
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Old 20th November 2012, 10:38 AM   #29
AndrewT is offline AndrewT  Scotland
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Originally Posted by CBS240 View Post
Refer to page 7 of Bob's Mosfet paper. It is a good illustration.
P7 shows the oscillation topology.
P11 shows a Zobel from Gate to audio ground.
Where is the Zobel you refer to?
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Old 20th November 2012, 11:16 AM   #30
MiiB is offline MiiB  Denmark
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I have seen some use a ferrite bead on the gates. this should elevate the stopper impedance with frequency and thus align the N and P Mosfet rolloff (speed)
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