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8th June 2012, 12:44 PM  #41  
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Join Date: Nov 2010

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I certainly plan to run the IPS and VAS near Ft max currents in my new amp. I have not actually seen this explicitly stated as an optimisation rule, can I claim it? Best wishes David 

8th June 2012, 01:03 PM  #42 
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Join Date: Jul 2003
Location: Taipei, Taiwan

I think running high IC for noise optimization and or selecting for Ft maximization are not new. IC designers do it all the time, although with some of the newer processes they are much less constrained than they were in the past.

8th June 2012, 01:13 PM  #43 
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As pointed in your PDF symetrical differentials allow for 6db higher gain.
Due to the two sides working in parralel in AC mode noise is also reduced by a 3dB factor compared to a single differential.. As for current , well i use 1 to 2mA or so for the input differentials and no more than 3mA for the VAS since this allow using low power devices with very high gain that will reduce IPS loading even without beta enhancer. 
8th June 2012, 01:31 PM  #44  
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Another scheme is the use of cascoded driver but not just any cascode, so called Hawksford. This I havent been able to stabilize either but it must be possible as Accuphase use it in their amps since 1990 upto now. This promises improved high frequency distortion which is where the problem really is. 

8th June 2012, 03:11 PM  #45  
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This has the potential to improve stability or increase feedback. Perhaps not relevant to simple Miller compensation but more so for input inclusive and similar advanced schemes. So my heuristic (as Bob Cordell says) is to pick the collector current and then use that as a point to drive the design. It will determine the Re of course, and probably need a cascode on the IPS just to keep dissipation tolerable, for example. And it may even be a little more than optimum for noise, but it should be analysed not just lazily defaulted to some "traditional" value. To be fair to D. Self he does analyse this for noise but not Ft AFAIK. And I like your term that you run "rich" Best wishes David Last edited by Dave Zan; 8th June 2012 at 03:37 PM. 

8th June 2012, 03:35 PM  #46  
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Bode showed that the ultimate limit is the speed of the devices, so I plan to run fast then see about the consequences. An input cascode allows low power/excellent Hfe devices and still run plenty of current. A beta enhancer is fine too. Best wishes David 

8th June 2012, 03:55 PM  #47  
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Analog design, The current mode approach. 

9th June 2012, 12:14 AM  #48 
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Location: Taipei, Taiwan

I agree if you run at currents that maximize Ft and minimize noise, you should be able to improve th design, provided other problems of course are not introduced.
Of bigger concern for me though is the behavior of the VAS stage with frequency (Cob) and the output stage hfe and Ft. Under heavy dynamic signals and a load that at any instant  due to the instantaneous frequency may be at 2 ohms and the next at 15, there's a lot going on. You have Ft bouncing around all over the place (take a look at the Ft vs IC curves on the 1302/1381 or similar devices), hfe doing the same and of course, if the VAS transistor has not been selected carefully (or a suitable topology used), Cob is also varying, and along with it some of the parameters I already mentioned. So, the combo of these things creates quite a cocktail and a good design has to make sure none of them impact performance. 
9th June 2012, 01:53 AM  #49  
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The maximum point naturally occurs where the slope is flat and so least sensitive to variations. Optimum value AND insensitivity is nice! For an output this implies a quiescent that then drives the value of Re pretty low, limited by thermal stability mainly. A practical quiescent will be below the max Ft value so the number of output devices can be chosen so that at maximum load the current per device is at the maximum Ft value and this should move stability in the correct direction. Your amp looks nice in this respect. Of course more quiescent and lower peak current will reduce the variation of practically any parameter. This is my idea on how to optimize this. It implies more current for the IPS, VAS and outputs than is commonly used and I am curious why. Best wishes David Last edited by Dave Zan; 9th June 2012 at 02:01 AM. 

9th June 2012, 06:46 AM  #50 
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Join Date: Jul 2003
Location: Taipei, Taiwan

One way to visualize this is on a 3 axis plot  Io, hfe and Ft. Would be nice to add a 4th dimension  phase margin. The instantaneous value of these parameters would be hopping around all over the place!

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