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Old 6th June 2012, 02:30 PM   #31
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Quote:
Originally Posted by Bonsai View Post
Interesting Homemodder. I never heard much about mirrors peaking as well (do you have link or can you point me in the right direction?). I am certainly now much more attuned to the possibility of these kinds of problems following mt experience with the cascode.

I would never have caught the cascode oscillation without my wideband scope BTW. Invaluable for audio
I was unaware of this as well but found it when I was looking for a second reference regarding the cascode peaking. Its a book from the early 90s. Give me a day or two and Ill try get the relevant page into electronic form and post it here. Maybe better if I email it to you, probably copyrighted.
The wilson mirror is the worse culprit with the beta enhanced and plain mirror less affected. The beta ehanced has however half the bandwith.
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Old 6th June 2012, 02:36 PM   #32
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Originally Posted by Dave Zan View Post
Very impressive work and very professional in every respect, not least the PDF. A pleasure to read a balanced and considered analysis in an audio publication
Did you consider a triple with CFP + EF? Self shows this and says it looks to have promise. Seems to me that it would be easier to thermally compensate than a triple EF. And I think the distortion should be even a little lower. I note Roender used one with success but I am surprised it is not more common.
Of course I haven't tried to stabilize one yet so I may learn.
My respect for your work and thanks for an informative analysis.

Best wishes
David
I have used cfp prediver in a triple EF but only with Mosfet output transistors. Using BJTs I couldnt get it stable, gain was probably too high. Useful to research it though, with mosfets THD was lower, enough to make the use extra transistors worthwile. In commercial products the use of darlington predrivers can be seen.
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Old 7th June 2012, 06:00 AM   #33
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Originally Posted by homemodder View Post
I have used cfp prediver in a triple EF but only with Mosfet output transistors. Using BJTs I couldnt get it stable, gain was probably too high. Useful to research it though, with mosfets THD was lower, enough to make the use extra transistors worthwile. In commercial products the use of darlington predrivers can be seen.
Do you mean a triple EF where the predriver is actually a CFP pair (so 4 transistors)
or a CFP predriver(+driver) then EF output?
What was the instability and what did you try to stabilize it?
And this was not a simulation but a real amp with what transistors?

Best wishes
David
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Old 7th June 2012, 03:28 PM   #34
Bonsai is offline Bonsai  Taiwan
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A correctly biased EF3 at mid powers gives about 0.1% open loop distortion, and about 0.8% at high power i.e at 5 to 10 % below clipping. Question is what do other output configurations deliver?
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Old 8th June 2012, 09:09 AM   #35
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Originally Posted by Bonsai View Post
A correctly biased EF3 at mid powers gives about 0.1% open loop distortion, and about 0.8% at high power i.e at 5 to 10 % below clipping. Question is what do other output configurations deliver?
Very reasonable question! I need some new hardware on the PC before I can run any more sims. But my tentative conclusion is that the CFP+EF is lower distortion than 3EF. But absolute numbers will obviously depend on exactly what "mid power" and exactly how far below clip, not to mention models, details of FFT etc. and perhaps simulator. I would be very interested in your results as to how the two versions compared, with your own specific set of assumptions.

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David
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Old 8th June 2012, 09:58 AM   #36
Bonsai is offline Bonsai  Taiwan
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Important also to do these sims considering how the load impedance varies as well. Real world loads are rarely 8 ohms. Another issue is bandwidth and where the HF poles are sitting.
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Old 8th June 2012, 11:48 AM   #37
wahab is offline wahab  Algeria
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Simulation give quite good results notably very low THD and IMD
as well as high slew rate.

There s a few pictures below that must be of course taken with
a big grain of salt since it s only simulations albeit this will give
an accurate view of the general trend.

I d like to add a few observations for the sake of the technical discussion.

Providing an LR output filter is used stability seems good ,
in fact even without such a filter it is not easy to make it ring
other than marginaly using a relatively high capacitive load,
so it seems that the triple EF compensation work very well.

There s voluntarly high standing currents in the front end , something
that is advocated by R.Cordell for the VAS but in that case so much heat
is not needed since this stage is loaded by a triple EF that render useless
high drive currents.

The input differential current is high and all the thermal dissipation burden
is devoted to the common base pairs since the common emitter differential
has only 7.5V Vce , a value that will maximize its Cbc , 20V being necessary
to bring it close to its minimal value wich will also reduce the common base
stage TDP notably.

Enhanced VAS does not bring as much improvement as it would if a current
mirror was used in the source for obvious reasons but it help reduce THD by a few dB.

Cascoding the VAS would reduce LF THD to single digit ppm ratios but it
would lefts THD unchanged at 10khz or above while endangering stability
by a sizeable margin so it wont be missed , moreover with the already
very low distorsion ratios.

Anyway , a pleasant amplifier that is really high definition.



.
Attached Images
File Type: gif BONSAI EA THD1-graph.gif (33.8 KB, 237 views)
File Type: gif BONSAI EA THD10-graph.gif (35.4 KB, 179 views)
File Type: gif BONSAI EA IMD047-graph.gif (34.4 KB, 180 views)
File Type: gif BONSAI EA IMD1920-graph.gif (30.1 KB, 177 views)
File Type: gif BONSAI EA SR-graph.gif (20.4 KB, 174 views)

Last edited by wahab; 8th June 2012 at 11:50 AM.
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Old 8th June 2012, 12:16 PM   #38
Waly is offline Waly  United Kingdom
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Quote:
Originally Posted by wahab View Post
The input differential current is high and all the thermal dissipation burden
is devoted to the common base pairs since the common emitter differential
has only 7.5V Vce , a value that will maximize its Cbc , 20V being necessary to bring it close to its minimal value
There is no Cbc minimum. Starting from 1 volt and up to the junction breakdown voltage, Cbc decreases with SQRT(Vbc). The only significant error in this sqrt law is around zero volts, where things are a little more complicated. With a very good approximation, at 20V each and every junction (BC, diode, etc...) will have a SQRT(20/7.5)~1.64 lower capacitance than at 7.5V. Classic Gray and Meyer textbook stuff.
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Old 8th June 2012, 12:16 PM   #39
Bonsai is offline Bonsai  Taiwan
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Thanks for the analysis Wahab.

I kept the front end cascode voltage low in order to minimize dissipation - a point you guessed correctly but perhaps one that I should have highlighted in my text. Certainly, running at a higher cascode voltage would also reduce Cbc. However, since the collector voltage of the input pairs are fixed by the cascodes, Cbc impact is substantially reduced.

Of course the high front end current facilitates high slew rates, and because the LTP is resistively loaded, must also support the current through them as well as drive Cdom. As I note in my text, the othe option is MIC, which by doing away with Cdom, will support very high slew rates. This gies the option then of running the front end at lower LTP currents.

A number of people's commented on the Ovation 250 that the VAS standing current was very high - a point I concede. This design is much lower, but I still prefer to run it 'rich'. I guess this is where as a designer you have the latitude to do things a bit differently. In the simulations, I looked for minimum modulation of the VAS standing current and looked at output loads from 2 to 8 Ohms.

Output Inductor. Yes, the e-Amp comp is conservative with plenty of room even driving quite a heavy capacitive load. But, I always think about the worst case scenario of a 2uF electrostatic hanging off the output. Note also that in TMC comp mode, the phase and gain margin are lower.

There seem to be a lot of harmonics on your distortion plots :-)
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Last edited by Bonsai; 8th June 2012 at 12:20 PM.
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Old 8th June 2012, 12:24 PM   #40
wahab is offline wahab  Algeria
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Originally Posted by Waly View Post
There is no Cbc minimum. Starting from 1 volt and up to the junction breakdown voltage, Cbc decreases with SQRT(Vbc). The only significant error in this sqrt law is around zero volts, where things are a little more complicated. With a very good approximation, at 20V each and every junction (BC, diode, etc...) will have a SQRT(20/7.5)~1.64 lower capacitance than at 7.5V. Classic Gray and Meyer textbook stuff.
The minimal value is at Vbc max of the device , isnt it ?...

Since this is a Sqrt law the reduction of Cbc over 10V start to become
marginal with increased Vbc , hence increasing Vcb to 20V , wich will
give a marginal improvement over 10V value but it was also to balance
TDP between the two parts of the cascode.
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