ESP P3A Layout

[superR]

And with a proper PSU, thats better, noise dropped below -100dBu. Only 200Hz and 250Hz still pop out. 250Hz is in my reference loop too so that contribution is not due to the amplifier.

[AndrewT]

Look at the hum and buzz. Most of that is due to connecting your 5 tappings into different voltages.
Some of it is due to connecting the Signal Ground to the Power Ground.

[superR]

Is the idead behind the layout from post 50 correct?
ESP P3A Layout

[AndrewT]

I cannot make out what is happening under/over Q7. I'm guessing the other device is Q8.
Six displaced tappings in that ground is worse then five.

[superR]

Then how about a top-groundplane? What are the disadvantages of that?

[currentflow]

Originally Posted by superR

Then how about a top-groundplane? What are the disadvantages of that?

Take a look at the PCB in the attachment of post #188 in this thread:
diyAB Amp - The "Honey Badger"

This PCB layout has been developed by several experienced members and might well serve as a guide.

[superR]

Well it's hard to keep the ground traces close and short, while I was advised earlier to keep the power and voltage stage far apart.....
In the picture below all high current stuff is at the top half of the pcb en the low current components are on the lower half. Top two connectors are for power and ls gnd.
The components above Q7 and Q8 can be placed there since the transistors go underneath the pcb.

[currentflow]

A couple of points I can see:

1) The signal ground trace running up the RH side of the board meets with two decoupling capacitors before reaching the 0V terminal point. As AndrewT stated in post #47: "When a current passes from +ve decoupling ground to Power Ground and when current passes from -ve decoupling ground to Power Ground there will be a voltage drop along the trace joining these decoupling capacitors together". You are sharing a section of this trace between signal ground and the rail decoupling. My suggestion would be to join the signal ground trace to a point nearer to the 0V terminal, even if it has to travel slightly further. Keep this trace separate to that which connects to the decoupling caps.

2) You have thick traces connecting the emitters of the output transistors to the rails, yet thinner ones connect their collectors to R13, R14. The amount of current will be nearly the same between the collectors and emitters.

[currentflow]

Also "C+1" 100nF near to Q2, another rail decoupling capacitor, decouples V+ to signal ground. Not a good idea!

[Rudi_Ratlos]

@SuperR,

a typical layout of mine looks like this:



and follows these guidelines:

- the positive power-rail is on the left side, the negative one on the right side
- the power caps are placed as near as possible to the output capacitors
- the taps to the power-rails for the frontend lie immediately behind the fuseholders
- the signalGND is tapped from the power-GND connector

I hope that this picture inspires your current work.

Best regards - Rudi_Ratlos