In the attached simplified schematic, C2 stabilises the global feedback loop (closed by R3), but how does one predict whether the feedback loop formed by C2 around the two JFETs will be stable? I would use the same type of JFET in both positions, or the same family sorted for different Idss.
Attachments
- Status
- This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.