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Old 25th April 2012, 07:08 AM   #1
3n2323 is offline 3n2323  United States
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Default LTspice / newbie question

(did't find a newbie forum to post, please move or delete if need to.)

i was playing with LTspice, and got the following result that i don't understand...

this was the circuit i used:
Click the image to open in full size.

the waves looked like this:
Click the image to open in full size.

suppose we:

take Vc to mean, voltage at collector relative to ground, and
take Vb to mean, voltage at base relative to ground, and
the condition for saturation is, when Vc < Vb, in other words, base-collector junction is forward biased.

then, when the collector curve goes below that of the base, that's when Vc is < Vb, the transistor should go into saturation, and no longer respond to signal -> constant -> flattened out at the bottom of the curve.

this will happen regardless of the fact that the lowest Vc is around 2.7V, way higher than the datasheet Vc(sat) ~= 0.2V, because saturation WILL happen when Vc < Vb. when this condition is met, saturation will happen first, then the Vc(sat) settles at around 0.2V; not the other way around, Vc reaches ~0.2V, then saturation happens and, as long as Vc is above ~0.2V, no saturation will happen.

but that's not the case, LTspice drew the whole cmoplete curve, no saturation.
i couldn't figure out why,
why LTspice is right, and
why i'm wrong.

please help me finding out where i made a mistake in my reasoning, thank you all!
Attached Images
File Type: jpg circuit.jpg (63.8 KB, 142 views)
File Type: jpg wave - Copy - Copy.jpg (114.6 KB, 138 views)

Last edited by 3n2323; 25th April 2012 at 07:32 AM.
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Old 25th April 2012, 08:02 AM   #2
godfrey is offline godfrey  South Africa
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The collector voltage can go below the base voltage. The transistor only saturates when the collector voltage gets close to the emitter voltage.

In your case, the saturation voltage is 0.2V, but that's the voltage between collector and emitter. Normally it is abbreviated as Vce(sat), not Vc(sat). When your collector voltage drops to 2.7V, it is still 0.3V above the emitter voltage, so no saturation. If you increase the input signal a little, you will see the saturation.
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Old 25th April 2012, 04:34 PM   #3
AndrewT is offline AndrewT  Scotland
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There are a couple of current LT spice Threads running.
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Old 25th April 2012, 05:40 PM   #4
Jay is offline Jay  Indonesia
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Quote:
Originally Posted by AndrewT View Post
There are a couple of current LT spice Threads running.
Yeah it would be nice if there is "Any Questions Regarding To LTSpice" thread dedicated to ANYONE who wants to ask questions.
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Old 25th April 2012, 05:54 PM   #5
cbdb is offline cbdb  Canada
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This thread needs to go in the software forum.
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Old 25th April 2012, 06:21 PM   #6
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Vce(sat) is specified at carefully controlled conditions. The NXP data sheet specifies Vce(sat) at Ic 10mA, Ib 0.25mA and Ic 50mA, Ib 1.25mA. The transistor is running less than 1mA in your simulation.

When I worked at a semiconductor company they had a trick question to ask prospective engineers. A grounded emitter transistor has only a capacitor conected between the collector and 5V. What voltage will the capacitor charge up to when the transistor is biased on? 5V - Vce(sat)? Wrong! The answer is 5V. As current falls to zero, Vce falls to zero.
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Old 25th April 2012, 06:33 PM   #7
Mooly is offline Mooly  United Kingdom
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Quote:
Originally Posted by Loudthud View Post
When I worked at a semiconductor company they had a trick question to ask prospective engineers. A grounded emitter transistor has only a capacitor conected between the collector and 5V. What voltage will the capacitor charge up to when the transistor is biased on? 5V - Vce(sat)? Wrong! The answer is 5V. As current falls to zero, Vce falls to zero.
Interesting question. I haven't tried it (I might ) but my instant thought is that the answer is incomplete. I don't think I'd initially trust LTspice for that either (for no good reason).

" As current falls to zero, Vce falls to zero
The current will fall to zero no matter what the collector volts is. If the collector is at 3 volts the current still falls to zero. If you measure using any "normal" meter then that will also provide a current path to charge the cap and consequently bring the voltage "to zero". So you would need a VOM or FET type meter.

I don't know the answer... just thinking aloud.

Zero as 0.00 volts. I'll think about that
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Old 25th April 2012, 08:15 PM   #8
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Rather than looking at Vb and Ve, plot the difference between them i.e. Vbe = Vb - Ve
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Old 25th April 2012, 08:25 PM   #9
3n2323 is offline 3n2323  United States
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Quote:
Originally Posted by godfrey View Post
The collector voltage can go below the base voltage. The transistor only saturates when the collector voltage gets close to the emitter voltage.

In your case, the saturation voltage is 0.2V, but that's the voltage between collector and emitter. Normally it is abbreviated as Vce(sat), not Vc(sat). When your collector voltage drops to 2.7V, it is still 0.3V above the emitter voltage, so no saturation. If you increase the input signal a little, you will see the saturation.
thank you godfrey, i got your point!

you are saying having base-collector forward biased is merely a necessary conditon for saturation, but not a sufficient one. every book i read talks about the three operating modes, and all emphasis is on the "base-collector forward biased" condition. Vce is played down, and only mentiioned as an "oh by the way".

anyways, following your suggestion, i tried it out again with a 5V input signal.

Click the image to open in full size.
it clipped like crasy. 5V, just to get the whole collector curve in the picture.

Click the image to open in full size.
in this picture, the transistor climbed out of saturation when the signal decreased to below Vc and. it went into saturation when the signal increased to above Vc, but then saturation will not necessarily happen, only when the signal kept increasing to where Vc would decrease to where Vce~=0.2V, will saturation be realized. so the saturation determining condition is really just Vce~=0.2V, and the base-collector forward biased condition is only getting the transistor heading that way with no guarantee of saturation. the Vce(sat) notation makes sense now. did i get it right this time?

Click the image to open in full size.
now, there is no abrupt transistion from normal operating mode to saturation mode, correct? if so, the two edges in this picture should still be part of the output sine wave, instead of abrupt theoretical straight vertical lines, correct?

also, the bottome edge of the output wave form has an upward bulging to it. it is in phase with the signal, so it can't the transistor is still trying to amplify. why the bulge, the transistor is in saturation there, it shouldn't have any response to the signal, what is it doing there?
Attached Images
File Type: jpg clips.jpg (129.3 KB, 81 views)
File Type: jpg sat.jpg (160.0 KB, 81 views)
File Type: jpg bulge.jpg (113.3 KB, 81 views)
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Old 25th April 2012, 08:29 PM   #10
Mooly is offline Mooly  United Kingdom
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Quote:
Originally Posted by Mooly View Post
I don't know the answer... just thinking aloud.

Zero as 0.00 volts. I'll think about that
I've just done a quick Spice file and it seems to show the collector volts as settling at around 17mv or so. The value depends on base current and transistor. That's kind of what I would have expected tbh although I would have guessed at Vc being a little higher than spice shows.

I'm a novie with spice and it took me a while to figure out how to get the results I was expecting. Had to set various delays in the supply voltage and bias but it works OK doing that.
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File Type: zip DC Test.zip (595 Bytes, 2 views)
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