Any one still remember Edmond's front end
Well I still need an OPS for it and I have a question.
How close to minimum phase is a BJT near Ft?
In the LTSpice help they call TF the "transit time"
If it is a real time delay then behaviour near Ft will depart from minimum phase.
If TF is just the time constant of the frequency roll-off then it will be close to minimum phase.
So a second question would be -
How close is SPICE to real transistor behaviour in this area?
This puts an upper limit on loop stability so it's fairly important for optimized compensation.
Best wishes
David
To say it short , mosfets are better in this respect.....
Hi David,
Did you read these comments , where I stated that a clear distinction should be made between time delay and phase lag? Or is it just a coincidence?
It occurs to me that the time delay in the various parts of the amp is a useful way to think about the optimization problem. The actual time delay sets an easily calculated limit to the maximum possible feedback. Time delays are simply additive so the maths should be easy. I expect someone has formulated the multi-loop feedback problem in this way, anybody know a reference?
Best wishes
David.
different beasts
Hi David,
The reason I emphasized on the difference between propagation delay and phase lag is because some people (NFB haters, for example) erroneously think that in an amplifier the FB signal should always come 'too late', i.e. time delayed and therefore it should be bad.
As also explained by Jan , this isn't the case. For this reason I prefer (and recommend) to think in terms of phase lag or phase delay. Also in mathematical sense phase lag (e.g. (1-exp(-sT))/s) and time delay (exp(-sT)) are two different beasts.
Cheers,
E.
Hi David,
The reason I emphasized on the difference between propagation delay and phase lag is because some people (NFB haters, for example) erroneously think that in an amplifier the FB signal should always come 'too late', i.e. time delayed and therefore it should be bad.
As also explained by Jan , this isn't the case. For this reason I prefer (and recommend) to think in terms of phase lag or phase delay. Also in mathematical sense phase lag (e.g. (1-exp(-sT))/s) and time delay (exp(-sT)) are two different beasts.
Cheers,
E.
Yes I understand this, I ended up in software but I studied mathematical physics*
That's why I asked about how close a transistor is to minimum phase. I really do mean the actual delay - of perhaps 5 or 10 nanoseconds for the OPS. This ultimately limits the amount of feedback because it creates excess phase that can not be phase compensated.
The anti-NFB people have an idea that contain some truth - that time delay matters. They misapply the idea because they don't understand the difference between time delay and phase shift. In the attempt not to confuse them a useful concept is avoided. Perhaps if we use it correctly it will actually over-ride the incorrect use and help.
But that's not my reason. Time delay is a conservative quantity so I think it will make it easier to optimize my circuit.
Best wishes
David
*And a lot of maths and stuff, thanks to Australia's absurdly cheap universities at the time. Wasted my chance to do more EE.
Last edited:
Add to that that is impossible to measure this delay (is it? or just nobody cares?.
I also wonder, since people can hear jitter of few dozens picoseconds, these few nanoseconds of delay in the OPS should be recognizable as well. Maybe less since we are dealing with higher level signals, but still...
And, if we just exclude the OPS from the feedback loop, the NFB of the previous stages (assuming is multistage) of which order of magnitude is?
just my 2c from a non EE
Hi David,
As for the actual delay in MOSFETs or BJTs, I really don't know how much it will exactly be. I guess it depends on the mobility of the electrons (or holes) and the distance they have to travel from source to drain, respectively from emitter to collector.
Ovidiu (syn08) should be able to answer this question, as he is an expert in the field of modeling semi-conductors.
Cheers,
E.
As for the actual delay in MOSFETs or BJTs, I really don't know how much it will exactly be. I guess it depends on the mobility of the electrons (or holes) and the distance they have to travel from source to drain, respectively from emitter to collector.
Ovidiu (syn08) should be able to answer this question, as he is an expert in the field of modeling semi-conductors.
Cheers,
E.
It occurred to me that a way to explain it would be to show a phase shifted output and then equalize the phase shift out of it - to show that it is completely restored and there is no delay. Since we don't have a minus delay time machine in the equalizer then there never was a delay in the output.
As to my hope that
Perhaps if we use it correctly it will actually over-ride the incorrect use and help.
It didn't work in time
And thanks for the reference to Ovidiu
Best wishes
David
Last edited:
Add to that that is impossible to measure this delay (is it? or just nobody cares?.
I also wonder, since people can hear jitter of few dozens picoseconds, these few nanoseconds of delay in the OPS should be recognizable as well. Maybe less since we are dealing with higher level signals, but still...
And, if we just exclude the OPS from the feedback loop, the NFB of the previous stages (assuming is multistage) of which order of magnitude is?
just my 2c from a non EE
Hello Telstar
Jitter is not delay, its caused by the noise of the of the oscillator (clock) at close in offsets.
Regards
Arthur
Seems that you and Jan have not
been able to make them understand over in that thread!While there I saw the thumbnail of your current SuperTIS and I noticed there is not a TPC load on the super-pair, as recommended in Fig. 6 on your website. Any particular reason or you just decided to keep the circuit "simple"
Best wishes
David
Seems that you and Jan have not
Indeed, that was a rather frustrating experience: explaining something "pour les couilles du pape".
BTW, is there anybody who can translate this French saying? Perhaps Jan? (hint, in Dutch we say: 'voor de kat z'n kut')
While there I saw the thumbnail of your current SuperTIS and I noticed there is not a TPC load on the super-pair, as recommended in Fig. 6 on your website. Any particular reason or you just decided to keep the circuit "simple"
Best wishes
David
It was a matter of trade-offs between phase margin of the Miller loop and distortion and finally I decided to let stability prevail.
In addition, I've changed the frequency compensation of the OPS to a 2nd order thingy.
Now, THD20k is below 1ppm, at least, according my sim.
Cheers,
E.
Litteraly , for (the sake of ) the pope s balls....Indeed, that was a rather frustrating experience: explaining something "pour les couilles du pape".
BTW, is there anybody who can translate this French saying? Perhaps Jan? (hint, in Dutch we say: 'voor de kat z'n kut')
On another side , i checked Hitachi s laterals modeling.
It is indeed a power law that is used as approximation ,
the subthreshold is not modeled , BUT , below threshold
there s simply no conduction , so the model will undoubtly
yield more distorsion than in real world , particularly for
higher ranges harmonics.
So even the strongest feedback loop can be unconditionally unstable unless you fool it somehow. If Tf is a time delay phenomenon, no amount of compensation can overcome this.
Sometimes I wonder why many designers go for the biggest, slowest outputs rather than paralleling smaller faster ones. The only benefit I can see is space and maybe total device capacitance. These devices are slower, and compensation can't overcome this (not easily anyways). Smaller outputs with higher Ft will not get any slower when paralleling, so you end up with more stability at higher bandwidth. For instance a pair of the MT-100 2SC3284 has better linearity, more speed, and more dissipation than the MT-200 2SC2922, and fits in the same space. Maybe total capacitance will be higher, but this can be compensated for. Maybe component count is another drawback; but it is in return for better performance.
I think the importance of Cbc in EF stages may be overrated. Cbe is a much ignored parameter that often makes all the difference. Most discrete devices, running at ordinary operating points are in the Ft region dominated by the Cbe-transconductance time constant. For outputs this is especially important. Sanken has nice LAPT transistors with Ft of 50MHz at several amps, but Ft at 100mA, where the majority of amps are biased, is lower than 20MHz. What good is the increased Ft at high currents if the Ft at crossover currents is mediocre? Outputs with >20MHz Ft at 100mA, with not much rise in Ft over the current range may actually be more useful for audio because the GBWP is not moving so much, and anomalous oscillation at power extremes is less likely.
For these reasons I choose outputs based on low-current Ft. I try to find outputs with Ft over 20MHz at 100mA. The 2SC2837/A1186 are a good candidate for paralleled fast output stages, although by the datasheets they will appear to give less linearity than the C3284/A1303. I previously thought Japanese semiconductors were best in this category, but looking through the MJLx281/x302 datasheets, it seems they are actually the best available. I learned OnSemi has acquired Sanyo, so maybe this explains it.
Am I on the right track? BTW I'm not confusing delay and phase, though maybe I mix terms a bit.
Sometimes I wonder why many designers go for the biggest, slowest outputs rather than paralleling smaller faster ones. The only benefit I can see is space and maybe total device capacitance. These devices are slower, and compensation can't overcome this (not easily anyways). Smaller outputs with higher Ft will not get any slower when paralleling, so you end up with more stability at higher bandwidth. For instance a pair of the MT-100 2SC3284 has better linearity, more speed, and more dissipation than the MT-200 2SC2922, and fits in the same space. Maybe total capacitance will be higher, but this can be compensated for. Maybe component count is another drawback; but it is in return for better performance.
I think the importance of Cbc in EF stages may be overrated. Cbe is a much ignored parameter that often makes all the difference. Most discrete devices, running at ordinary operating points are in the Ft region dominated by the Cbe-transconductance time constant. For outputs this is especially important. Sanken has nice LAPT transistors with Ft of 50MHz at several amps, but Ft at 100mA, where the majority of amps are biased, is lower than 20MHz. What good is the increased Ft at high currents if the Ft at crossover currents is mediocre? Outputs with >20MHz Ft at 100mA, with not much rise in Ft over the current range may actually be more useful for audio because the GBWP is not moving so much, and anomalous oscillation at power extremes is less likely.
For these reasons I choose outputs based on low-current Ft. I try to find outputs with Ft over 20MHz at 100mA. The 2SC2837/A1186 are a good candidate for paralleled fast output stages, although by the datasheets they will appear to give less linearity than the C3284/A1303. I previously thought Japanese semiconductors were best in this category, but looking through the MJLx281/x302 datasheets, it seems they are actually the best available. I learned OnSemi has acquired Sanyo, so maybe this explains it.
Am I on the right track? BTW I'm not confusing delay and phase, though maybe I mix terms a bit.
Yes. In fact, the stronger the feedback, the more difficult to keep it stable. If you have an unstable amplifier you can almost always make it stable by decreasing the feedback (higher closed loop gain).
If you look at the data sheet for example for the LM3886 you will see a MINIMUM closed loop gain for stability - stronger feedback (lower closed loop gain) will make it unstable.
jan
Well in my head it was a bit unclear what a "strong" feedback loop was, and that was not the concept I was focusing on anyways. My thoughts were as simple as: phase shift can always be corrected; delay cannot; therefore a feedback loop "strong" enough to correct any amount of phase shift would still be unconditionally unstable if a time delay were introduced.
Another point on Ft is that transistors with high Ft at low currents evidently have low Cbe, and this means there is less hullabaloo trying to move charge in and out of the base during switching. So switching behavior will be better with fast signals, and the bias will not be so badly affected by parasitic oscillation.
Incidentally I just blew up a prototype local feedback output stage. It has the current gain of a triple EF, but without the voltage distortion. High order distortions are reduced by a lot. It worked as predicted while it was running, but I couldn't tell whether the bias drift was due to rail sensitivity or bad thermal compensation. One aspect of this circuit is that it has indefinite and very fast drive capability - it destroyed the outputs before they had the opportunity to smoke. I clamped the heat sensing diodes under the collector pins, and now I suspect this kept the outputs from mating with the heatsink properly. I don't want to post any schematic until I've fully explored it, but I thought it was notable because it behaved the way I expected it would, concerning stability. But this time I will add the protection circuit. It is exciting to take solutions discovered in simulation and apply them to real circuits, when one is finally able to do this.
Another point on Ft is that transistors with high Ft at low currents evidently have low Cbe, and this means there is less hullabaloo trying to move charge in and out of the base during switching. So switching behavior will be better with fast signals, and the bias will not be so badly affected by parasitic oscillation.
Incidentally I just blew up a prototype local feedback output stage. It has the current gain of a triple EF, but without the voltage distortion. High order distortions are reduced by a lot. It worked as predicted while it was running, but I couldn't tell whether the bias drift was due to rail sensitivity or bad thermal compensation. One aspect of this circuit is that it has indefinite and very fast drive capability - it destroyed the outputs before they had the opportunity to smoke. I clamped the heat sensing diodes under the collector pins, and now I suspect this kept the outputs from mating with the heatsink properly. I don't want to post any schematic until I've fully explored it, but I thought it was notable because it behaved the way I expected it would, concerning stability. But this time I will add the protection circuit. It is exciting to take solutions discovered in simulation and apply them to real circuits, when one is finally able to do this.
Incorrect. The absence of subthreshold conduction model will not make the distortion higher but lower. Due to the exponential Id-Vgs conduction law in the subthreshold region, the gm doubling distortion mechanism occurs, like in bipolars (with more high order harmonics, etc...). Otherwise, with only a power conduction law, the gm doubling distortion mechanism contribution is small.
This is again basic textbook stuff and applies to any mosfet type (not only laterals). If you want more proof, get the 2SK1530/2SJ201 level 1 and level 4 (developed by Andy_C) models and check it out for yourself.
Better an exponential variation at sub threshold than an abrupt
threshold wich will yield obviously way more high order switching
distorsion....
- Status
- This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.