I think phase shift must ultimately accumulate with ANY circuit.
By the time you add typical gate stopper resistors to MOSFETs I am not sure if the speed is so much better as to be worth the effort.
What I currently study is how fast I can make a conventional BJT OPS.
The NJL4*** transistors are nominally 35 Mhz Ft. Is the typical 1-2 Mhz unity crossover frequency really the best one can do?
Now the e-amp is finished you can start work on this
Best wishes
David
Hello Dave,
Check out the 2SA2040/2SC5707 (available from Mouser) - max current 8 amps, linear HFE vs. Ic up to about 3 amps, minimum HFE of 200, fT > 200 MHz for 100 mA < Ic < 2 A, Cob @ 10 V Vce 50/28 pF respectively. These are small transistors so have very small SOA - you would have to use several in parallel* in a rail-tracking amplifier (supply their power from a low-voltage floating supply whose midpoint is driven by a second amplifier; frequency response of two amplifiers must match very closely in the audio band).
* note five in parallel still gives under half the Cob of one MJL4302.
Check out the 2SA2040/2SC5707 (available from Mouser) - max current 8 amps, linear HFE vs. Ic up to about 3 amps, minimum HFE of 200, fT > 200 MHz for 100 mA < Ic < 2 A, Cob @ 10 V Vce 50/28 pF respectively. These are small transistors so have very small SOA - you would have to use several in parallel* in a rail-tracking amplifier (supply their power from a low-voltage floating supply whose midpoint is driven by a second amplifier; frequency response of two amplifiers must match very closely in the audio band).
* note five in parallel still gives under half the Cob of one MJL4302.
Dave/Harry
Yes, I agree bipolars are also an option.
For the mosfets, I think there has to be a lot more focus on layout to enable one to exploit more of the potential bandwidth. I am currently very involved in mostfet power switching and external layout is absolutely critical for clean switching (we are talking 2-3ns rise times and 10ns fall times). So, you have to treat the PCB layout of the output stage and the mosfets as a system.
C'mon Edmond, put your thinking cap on - but remember, 12 trannies max!
Yes, I agree bipolars are also an option.
For the mosfets, I think there has to be a lot more focus on layout to enable one to exploit more of the potential bandwidth. I am currently very involved in mostfet power switching and external layout is absolutely critical for clean switching (we are talking 2-3ns rise times and 10ns fall times). So, you have to treat the PCB layout of the output stage and the mosfets as a system.
C'mon Edmond, put your thinking cap on - but remember, 12 trannies max!
Thanks for the recommendation but breakdown Vce too low for me. I want to build a few amplifiers and a research project on rail trackers is just too much!
That is the reason I have chosen BJT. I have no experience in MOSFET and I don't need a research project there either! If you have the expertise then they probably have more potential.
And 12 trannies max? I plan to use that many just in each OPS!
JBL pro drivers
Best wishes
David
Hi Arthur
Yes 6 PNP & 6 NPN outputs + pre drivers and drivers so 16 in total. 3 kilowatts of On semi's finest transistors. No HEC, don't need another research project there either! I think Andrew's (Bonsai) and Dadod's amps (for instance) show you can obtain distortion that is below any reasonably audible threshold with conventional OPS and just advanced compensation. The advanced compensation is as much research as I need. Any one want to start a study team on Lurie's "Classical Feedback Control"?
Best wishes
David
BTW. Where are you in Oz?
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One conventional method I see used by accuphase to remedy the bandwith situation is the use of cascoded drivers. Its also not just conventional cascode but they use a hawksford type cascode on their drivers. I have experimented with it but so far I am unable to get such a setup stable, I still dont know how they manage it but theyve been at it since the 90s so there must be a way. Maybe someone has a schematic of later year model, I would be interested in seeing it. Any comment on how much this could improve matters ??
From the literature they have on their amps. They show simplified schematic and describe the circuit on nearly all their amps but not the fine details. It works to a certain extent, I have tried on a blameless the problem arises with oscilation and to a lesser extent the temp compensation which gets affected as well. No matter what I have tried Ive failed to get it stable.
Hi Andrew,
Since MOSFETs are faster than BJTs, I think that's the way to go, at least in principle. BUT... MOSFEts not only exhibit higher distortion, they also need gate stoppers, which limit the effective bandwidth. So, for higher BW (and lower THD) its crucial to make the gate stoppers as small as possible. The game is here how far you can go in making them smaller. That depends, as you already remarked, on the PCB layout, i.e. parasitic stray inductances and capacitances. Now I wonder whether it is sufficient to use a four layer PCB with just simple power and ground planes and abundantly decoupled with multi layer ceramic caps?
Although MOSFETs basically exhibit higher distortion than BJTs, it doesn't necessarily mean that when used in a class AB output stage, the distortion will also be higher. Opposed to a class-B BJT OPS, the overlapping region where both P and N channel devices are conducting, is much wider. As a result, the spectral content of the cross-over distortion is limited to lower frequencies and (because of more loop gain) easier to suppress by means of NFB.
So who will win? BJTs or MOSFETs?
>but remember, 12 trannies max!
Including the trannies inside the ICs?
Not an easy job!
Cheers,
E.
NDFL
Hi David,
BTW1, here's another implementation of NDFL + TMC. See X1, C3...C7, R14, R16, R18...R20.
The stuff around the op-amp looks like the front-end of the Alexander amp, though it isn't.
BTW2, NDFL amps are not that easy to implement, as they suffer from bad recovery from overload conditions. That's the reason why in the PGP amp as well in the Phoenix amp, active feedback clamps have been applied. In case of the PGP amp, this works very well, however, in case of the Phoenix amp, it appears troublesome to make such a clamping feedback loop sufficiently stable (that's also the main reason why this project has not been finished yet).
Cheers,
E.
Hi David,
BTW1, here's another implementation of NDFL + TMC. See X1, C3...C7, R14, R16, R18...R20.
The stuff around the op-amp looks like the front-end of the Alexander amp, though it isn't.
BTW2, NDFL amps are not that easy to implement, as they suffer from bad recovery from overload conditions. That's the reason why in the PGP amp as well in the Phoenix amp, active feedback clamps have been applied. In case of the PGP amp, this works very well, however, in case of the Phoenix amp, it appears troublesome to make such a clamping feedback loop sufficiently stable (that's also the main reason why this project has not been finished yet).
Cheers,
E.
"I will read Ed Cherry and hope for a better idea."
I don't think NDFL is optimal, even aside from problems with overload recovery.
I am not actually very concerned about clip behaviour. 115 dB sensitive JBL compression drivers so practically unlimited headroom. If they clip when you are at a reasonable distance then you have much worse problems.
Best wishes
David
I don't think NDFL is optimal, even aside from problems with overload recovery.
I am not actually very concerned about clip behaviour. 115 dB sensitive JBL compression drivers so practically unlimited headroom. If they clip when you are at a reasonable distance then you have much worse problems.
Best wishes
David
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Not entirely correct. This was analyzed to death in the CMOS linear IC literature: while indeed mosfets, compared to bipolars, do not exhibit the gm doubling effect, for the particular case of discrete power mosfets that doesn't help much. The subthreshold conduction (where Ic vs. Vgs is exponential, like in bipolars) extends to 100 mA or even more. This is one of the reasons why mosfet output stages need much heavier bias compared to bipolars.
But the big trouble with mosfet distortions appears when Vdg approaches zero (that is, when the output approaches the power supply rails). Then the Cgd for vertical devices (the equivalent of Cob for bipolars) increases dramatically and also it's heavily modulated by the signal. This may of course be in part alleviated by allowing generous output swing reserves (like +/- 60V supplies for 100W/8ohm) but this affects the overal power dissipation.
Otherwise, compared to bipolars, although mosfets definitely may have slightly better crossover distortions, the total distortion are significantly larger, for any practically realistic class AB bias and power dissipation.
And finally, it is not realistic to think of a mosfet output stage with much higher unity gain frequency compared to bipolars. It can be build higher, but not dramatically higher. That's because switching and linear applications have totally different set of constraints, in particular related to power dissipation. While for switching (with essentially very low conduction losses) devices or even chips can be crammed together to reach a minimum in parasitic inductances, and hence minimize switching losses, for linear application it is totally wrong to believe that parasitic values can be anywhere close. Devices have to be spread over a large area to aloow heat to flow as much as possible uniformly over the heatsink.
As usual, it is easy to make things work in simulators, not so much in practice. Most mosfet models I've seen do not model the subthreshold region, and neither do they model correctly Cgd for small Vgd.
T0 leaded package parasitics, polySi gate resistance are some very high frequency operating limits
and has been addressed
IXYS RF: HF/VHF Linear MOSFETs
never seen any acutally motivated enough to try these in audio though
and has been addressed
IXYS RF: HF/VHF Linear MOSFETs
never seen any acutally motivated enough to try these in audio though
The PCB parasitic inductances totally dominate. That's one reason why modern SMPS' use SMD packages. Devices capacitances are another story of course and in both linear and switching applications they are problematic.
However, I think with regard to the output stage, they can be mitigated with error correction or a local feedback loop such that the FE sees a much more benign output stage load. As to the additional power dissipation, you just have to live with it - we are talking about distortion levels at sub 100ppb.
However, I think with regard to the output stage, they can be mitigated with error correction or a local feedback loop such that the FE sees a much more benign output stage load. As to the additional power dissipation, you just have to live with it - we are talking about distortion levels at sub 100ppb.
Why? Notice that I was exclusively talking about cross-over distortion, not other kinds of distortion.
Therefore, I asked myself: 'So who will win? BJTs or MOSFETs?'
Agreed.
Agreed and that's why my OPS keeps away from the supply rails by about 5 volts. It's also the reason why I don't bother using an elevated PSU for the front-end in order to squeeze the last watts out of the OPS.
Coincidentally, for the same reason I'm playing now (simulation wise) with lateral MOSFETs, which don't exhibit the nasty behavior of Cgd.
Agreed, see also my 1st comment.
Agreed.
I know this topic was once raised by JC (he is using BJTs), but I believe that it's less critical in case of MOSFETs (because of a lower dId/dT).
Also, a uniform heat flow over the heat sink in itself doesn't matter. What does matter is that the OP devices should be held at the same temperature. So, when they are put infinitely close together (not possible), then all devices will also have the same temperature.
Agreed. Happily I do have sub-threshold models for the 2SJ201/2SK1530 pair, but not for laterals like an ALF16P20 or ALF16N20. This makes a simulated comparison (of THD) between them virtually useless.
As for Cgd, I'm using diode models to mimic the capacitance. I'm aware of the shortcomings of such models, but as long as the min. and max. capacitances under dynamic condition are close to real values, I'm happy with it.
BTW, is there anybody who have decent (EKV) models for laterals?
Cheers,
E.
Unfortunately, they are now useless. That pair is dead and buried by the manufacturer (Toshiba).
There is no winner. The ultimate distortion performance, in any realistic implementation, and for the same stability margins, are virtually identical. It's a matter of preference, fashion, marketing, etc...
As a simulating only designer, I am surprised you prefer mosfets. Bipolar power device models are much better (and even much easier to improve, if one has the patience, passion and the right tools).
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The Hitachi/Renesas 2SJ162/2SK1058 lateral fets has excellent
caracteristics for audio , although i warmly recommend to use
two or three pairs.
As for accurate model , i checked the N channel one ,that seems provided
by the manufacturer.
Using a sawtooth as input signal , the device output , in common drain ,
exhibit a exponential or power law , i didnt check exactly at this time ,
at level from 0 to 0.1V Vgs.
caracteristics for audio , although i warmly recommend to use
two or three pairs.
As for accurate model , i checked the N channel one ,that seems provided
by the manufacturer.
Using a sawtooth as input signal , the device output , in common drain ,
exhibit a exponential or power law , i didnt check exactly at this time ,
at level from 0 to 0.1V Vgs.
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